The self-purging technique is not commonly used mainly due to the lack of practical implementations of its key component, the threshold voter. A very efficient implementation of this voter is presented which uses a decomposition technique to substantially reduce the circuit complexity and delay, as compared to alternative implementations.Comisión Interministerial de Ciencia y Tecnología TIC97-064

Avedillo de Juan, María José

Huertas Díaz, José Luis

Quintana Toledo, José María

English

idUS. Depósito de Investigación Universidad de Sevilla

EFFICIENT REALIZATION OF A THRESHOLD VOTER FOR SELF-PURGING REDUNDANCY1José M. Quintana, María J. Avedillo, and José L. HuertasInstituto de Microelectrónica de Sevilla, IMSE-CNM, Univ. de Sevilla.Edif. CICA, Avda. Reina Mercedes s/n, Sevilla 41012, SPAIN1This effort was partially supported by the spanish CICYT under Project TIC97-0648.Indexing Terms: Self-purging Redundancy, Fault Tolerance, Sorting Networks, Threshold Logic.Abstract:The self-purging technique is not commonly used mainly due to the lack of practical imple-mentations of its key component, the threshold voter. A very efficient implementation of this voteris presented which uses a decomposition technique to substantially reduce the circuit complexityand delay, as compared to alternative implementations.IntroductionAchieving ultrareliable systems is a goal of increasing importance in many areas. The self-purging hybrid approach [1] allows us to improve the reliability of digital systems and it has very sim-ple switching mechanisms, a straighforward design and is simpler, cheaper and more reliable thanother hybrid approaches. Also, the faulty modules can be replaced from the system without affectingthe normal operation of the system. This characteristic of self-purging systems is extremely attractivebecause it eases maintenance and repair.In the self-purging approach each of the N identical modules has the capability to disconnectitself from the system in the event that its output disagrees with the voted output of the system.Switches remove their associated module from the system in case the module fails. The voter pro-vides the mean for the masking of any fault that occurs in the module outputs. The voting is doneby means of a threshold gate. The choice of the voter threshold is critical for the tolerance of self-purging systems to multiple faults. In general, the best voter threshold is equal to half the numberof the remaining fault-free modules [1].In spite of the advantages described, the self purging technique is not commonly used infault-tolerant digital designs. One reason for this limited utilization is that it is difficult to con-struct a threshold gate because it is claimed as an analog element, which is not practical for dig-ital use. Concerning digital implementations, a direct implementation of the voter can be veryexpensive in terms of the number of gates [2]. Therefore, some simplifying solutions have beenreported. Razavi [3] substitutes the threshold gate with a digitally constructed “strong majorityvoter” which automatically adjusts its threshold. However, the system presented is of limiteduse because only single module failures per clock cycle are allowed. A solution which can tol-erate multiple module failures at any time is presented in [4], but no solution to build the voteris presented. In this paper a very efficient decomposition technique for the logic function per-formed by the voter is developed, allowing an extremely compact realization.The Losq VoterThe voter that produces the system output and provides fault masking is a threshold gate. Athreshold gate (TG) has n two-valued inputs x1, x2, …, xn and a single two-valued output, y. It isdefined by n+1 real numbers: threshold T and weights w1, w2, …, wn, being denoted as,where weight wi is associated with variable xi. The input-output relation of aTG is defined as y=1 iff and y=0 otherwise. Sum and product in the previous definitionare the conventional operations, instead of logical ones.The classical solution to the automatic threshold adjustment uses a simple mechanism asshown in Figure 1 [1]. The threshold voter is described as , and it has beenrepresented by a non-standard but widely used symbol.Implementing the Losq voter is a difficult task because the large number of inputs it exhibits.As weights for xi are 1 and weights for yi are 2, the total weight for the gate is 3N. The most eco-nomical solutions for implementing this kind of voters are based on sorting networks [2]. Thus, theLosq voter would require a 3N-input SN to be implemented.Proposed Voter ImplementationIn this section, an efficient and extremely compact decomposition technique for the logicfunction performed by the voter is developed.w1 w2 … wn T;, , ,[ ]wixi T≥i 1=n∑1 2 1 2 … 1 2 N;, , , , , ,[ ]Theorem 1: The output of the voter from a self-purging scheme with N replicated mod-ules can be obtained from a two-level network composed by two N-input SNs, and acombinational network L, with inputs, as shown in Figure 2a. The first SN de-pends on yi variables (i=1, ..., N), and the second one depends on xi variables (i=1, ..., N).Proof: Let us consider the Losq voter for N modules given by , i.e. the voteroutput is asserted if . Let us divide the input set into twodisjoint subsets, , and . Let andbe two quantities which will be very useful in the following. Input combi-nations which assert voter output L are:{(a or more variables in S1 are at logic 1) or(a-1 or more variables in S1 at logic 1) and (b or more variables in S2 at logic 1) or(a-2 or more variables in S1 at logic 1) and (b+2 or more variables in S2 at logic 1) or..............................................................................(1 or more variables in S1 at logic 1) and (N-2 or more variables in S2 at logic 1) or(N variables in S2 at logic 1)}This formulation yields the logic expression for the voter output:(1)where stands for a function which asserts when at least r variables in S1 are 1, and has asimilar definition but referred to S2. But this definition is exactly that corresponding to an N-inputthreshold function (inputs from S1 or S2) with all the N weights equal to 1 and threshold in r. Thereare of such TGs, of them depending on variables xi and another depending on variables yi.The fan-in of all of them is N, as shown in Figure 2b.The solution given in Figure 2a is obtained when the conceptual link between thresholdgates and SNs [5] is applied. An n-input SN is a switching network with n outputs which are asorted (non-increasing order) permutation of the inputs. The set of outputs in an n-input SN aren TGs corresponding to , where if , , and 02 N2----1 2 … 1 2 N;, , , ,[ ]xi 2 yi+( ) N≥i 1=N∑ x1 y1 … xN yN, , , ,{ }S1 y1 … yN, ,{ }= S2 x1 … xN, ,{ }= a N2----=b 2 N2----N2----–+=f L TY aNTY a 1–NTX bN⋅ TY a 2–NTX b 2+N⋅ … TY 1NTX N 2–N⋅ TX NN+ + + + +=TY rNTX rN2a a aT 1nT 2n… Tnn, , ,( ) Tmn 1= xii 1=n∑ m≥ m 1 2 … n, , ,=otherwise. Thus, the outputs from both sets of TGs in the first level shown if Figure 2b arespecific outputs of two SNs: one of the SNs sorts yi variables (i=1, ..., N) and the other sorts xivariables (i=1, ..., N). To evaluate the performance of both the traditional and the proposed solutions a compar-ison of their complexity and delay is in order. Concerning the complexity, the number of 1-bitcomparators (a 1-bit comparator is implemented by means of a 2-input AND gate and a 2-inputOR gate) needed in a n-input SN based on Batcher’s odd-even merge sort is given in [6]:(2)where is the number of comparators required to merge two sorted sequenc-es of sizes  and , given by:(3)and ,  and .Concerning the number of gate levels, the delay time in Batcher’s sorting method for nelements is given by:(4)When these expressions are applied to a self-purging redundancy scheme for N-modules,the cost of the voter is given by , and its delay is. In our approach, the cost of the voter is given by, is the cost of the combinational circuit at the out-put. The delay is , where delayCC corresponds to thecombinational output circuit. Figure 3a clearly shows the difference in complexity betweenboth solutions for typical values of the module number, N, and Figure 3b compares the delayfor both approaches for the same range of N. Delay of the combinational output circuits dependson the available gates. For a comparison, we have supposed that 4-input OR gates are available.N2----Csort n( ) Csort n2--   Csortn2--   Cmerge n2--n2--,   ; n 2>( )+ +=Cmergen2--n2--,  n2--n2--Cmergen2--n2--,   Cmergen2--2---------n2--2---------,     Cmergen2--2---------n2--2---------,     n2--1–+ +=Cmerge 1 1,( ) 1= Cmerge 2 1,( ) 2= Csort 2( ) 1=delay n( ) 1 log2n+2  =Cost1 Csort 3N( )=Delay11 log23N+2  =Cost2 2 C⋅ sort N( ) CostCC+= CostCCDelay21 log2N+2   delayCC+=Example 1: Let us consider the design of a threshold voter from a self-purging schemewith 5 replicated modules. The voter needed is , i.e., the voter out-put is asserted when .From definitions for in Theorem 1, we obtain and. A logical expression for the voter output in Eq. (1) gives:The sum-of-product for this function has prod-uct terms, of three, four and five literals. However, when the voter is implemented as a sortingnetwork, Eq. (2) gives a cost of 2-input comparators. The implementationobtained following the decomposition proposed in Theorem 1 provides a cost of2-input comparators plus the cost of the combinational circuit at the output,which can be implemented by two 2-input AND gates and one 4-input OR gate, as shown inFigure 4. Further reduction in the number of comparators in both SN-based solutions can be ob-tained by eliminating comparators which are not used, but exact figures do not substantiallymodify the above reasonings about complexity. Concerning the delay time of both the tradition-al and the proposed solutions, Eq. (4) gives time units forthe first implementation, and time units (5-input SN) plustwo time units (combinational part) for the proposed implementation. ConclusionsA low-cost implementation of the classical self-purging approach from Losq has beenproposed. It is based on both the application of a decomposition technique and the use of theconceptual link between TGs and SNs. The proposed implementation exhibits an excellent per-formance when compared to the original solution.1 2 1 2 1 2 1 2 1 2 5;, , , , , , , , ,[ ]xi 2 yi+( ) 5≥i 1=5∑a and b a = 52--= 3b = 2 52--52--–+ = 1f L TY 35TY 25TX 15⋅ TY 15TX 35⋅ TX 55+ + +=53   52   51  ⋅ 51   53  ⋅ 55  + + + 111=Csort 3 5×( ) 59=2 Csort 5( )× 18=delay 15( ) 1 log215+2   10= =delay 5( ) 1 log25+2   6= =References[1] J. Losq: “A highly efficient redundancy scheme: self-purging redundancy”, IEEE Trans.on Computers, vol. C-25, No. 6, pp. 569-578, June 1976.[2] B. Parhami: “Voting networks”, IEEE Trans. on Reliability, vol. 40, No. 3, pp. 380-394,Aug. 1991.[3] H.M. Razavi: “Self-purging redundancy with automatic threshold adjustment”, IEEProc.-G, vol. 140, No. 4, pp. 233-236, August 1993.[4] C.W. Chiou and T.C. Yang: “Self-purging redundancy with adjustable threshold for tol-erating multiple module failures”, Electron. Lett., 1995, 30, (11), pp. 930-931.[5] E.A. Lamagna, “The complexity of monotone networks for certain bilinear forms, routingproblems, sorting, and merging”, IEEE Trans. on Comput., vol. C-28, pp. 773-782, Oct. 1979.[6] D.E. Knuth, The Art of Computer Programming, Vol. III, Sorting and Searching, 2nd ed.Reading, MA: Addison-Wesley, 1973, ch. 5.FIGURES&⊕Module iFigure 1:Self-purging approach with N modules for optimal tolerance to multiple failuresswitch iInitializationand retry[1,2,...,1,2;N]12NQQ xiyiS R 1212voterxNyNx1y1Systemoutputfrom module Nand switch Nfrom module 1and switch 1y1yN11 aFigure 2: Two level realization of self-purging voter, (a) using SNs, (b) using TGsTaNTNNy1yNx1xNBb=TbNA1=T 1NAa=TaNBN=TNNSortingNetworkSortingNetwork(a) (b)Tb+2NTN 2–NT 2NTa 1–NLL x1xN11 bTbNx1xN11 Ny1yN11 1T 1NSystemoutputSystemoutputFigure 3: Cost parameters for the traditional and the proposed solutions(a) (b)0 5 10 1502468size of network in hundred of 2-input gatestraditionalproposednumber of modules, N0 5 10 150510152025gate levelstraditionalproposednumber of modules, N(a) Size of network in hundred of 2-input gates, (b) DelayFigure 4: Proposed realization for the self-purging voter in Example 1y1y5T 155-inputSN5-inputSNy2y3y4T 25T 35x1x5x2x3x4T 15T 35T 55&&+f L

Efficient realization of a threshold voter for self-purging redundancy

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Efficient realization of a threshold voter for self-purging redundancy

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