Association among Occupational Stress factors and Performance at workplace among Agricultural Research Sector Employees at Hyderabad, India

This study reports the results on the association among occupational stress factors and employee performance at workplace using a survey of 756 employees of agricultural research sector in Hyderabad Metro, India. The seven independent occupational stress causing factors shift work, working hours, high on job demand, lack of job control, social support, job insecurity, lack of salary rewards and the dependent variable employee performance measured. The data collected using the structured self-reported and undisguised questionnaire on agricultural research sector employees working in and around Hyderabad Metro. Using the questionnaire data was collected on general characteristics, health related issues using dichotomous variables and job characteristics – that is occupational stress factors using statements measured on a 5-point likert type scale. The chisquare test and multivariate logistic regression analysis were applied to measure to observe if any statistically significant association among the seven occupational stress factors and employee performance. The reliability of the scale used for the study and internal consistencies of the study instrument were measured using the reliability statistic Cronbach’s alpha (C-Alpha). The overall C-Alpha value for the measured at Men 0.83 and for women 0.79 and for all eight factors the C-alpha values ranged from 0.67 to 0.83 for Men and from 0.64 to 0.86 for Women. The results suggested that there was a statistically significant association between occupational stress factors like working hours/week (51-60 hrs, OR=1.41, 95% CI 1.09-1.71, p<0.01; >60 hrs/week, OR=1.94, 95% CI 1.65-2.44, p<0.01), job insecurity (OR=3.42, 95% CI 2.86-6.83, p<0.01 and social support (OR=4.42, 95% CI, 2.76-6.74, p<0.01)) effecting the performance. There are no significant differences were observed on odd rations in adjusted model

DESIGN OF 4-BIT MCC ADDERS TO IMPROVE PROCESSOR SPEED IN VLSI

Enhance the processer speed by diminishing the convey delay furthermore decreased the power utilization. The testing paradigm of profound submicron advancements is low-power and fast correspondence computerized flag preparing chips. The execution of numerous applications as advanced flag handling relies on the execution of the math circuits to execute complex Algorithms. Quick number juggling calculation cells including adders are the most often and generally utilized circuits as a part of extensive scale combination (VLSI) frameworks. More over decrease of the power utilization is the basic worry in this field. Presently now a days there is at colossal interest for compact electronic gadgets, the architects are headed to take a stab at littler silicon region, higher speed, and longer battery life. Viper is the center component of complex number-crunching circuits like expansion, duplication, division, exponentiation, et cetera. Static CMOS circuits comprised of a corresponding PMOS as draw up and NMOS as draw down networks. Majority of the circuit outlines are as yet utilizing this as it gives low commotion, low power and quick speed. The principle preferred standpoint of CMOS over NMOS and bipolar is much littler power dissemination. Rationed circuit supplanted the pull up PMOS arrange by associating it to a ground. By interfacing PMOS to a ground, there is an extraordinary diminishment in the draw up transistors utilized when utilized as a part of an unpredictable plan. Dynamic circuit is like ratioed circuit however the PMOS is attached to a clock. PMOS is not generally on as it is controlled by the deliberately arranged clock. Range, deferral and power are the three for the most part acknowledged outline measurements to quantify the nature of a circuit or to think about different styles of circuits. The most generally utilized rationale [1] style is static correlative CMOS. The static CMOS style is truly an expansion of the static CMOS inverter to various data sources. In audit, the essential favorable position of the CMOS structure is vigor (i.e., low affectability to clamor), great execution, and low power utilization (with no static power utilization). As we will see, the greater part of those properties are persisted to substantial fan-in rationale entryways actualized utilizing a similar circuit topology. In this work, we endeavor to address these weaknesses of utilizing DFTL as a part of rationale operations with an examination on the ideal measuring proportion and a "timing window" strategy. For correlation purposes, the vitality versus delay (E-D) conduct of indistinguishable 64-bit Sklansky convey combine tree executed in DFTL, CDL, dynamic rationale, and static rationale doors is broke down

THE METHODS OF IMPROVING THE SPEED OF CLA ADDERS IN DOMINO LOGIC

Adders are the critical parts of processor circuits. The performance of processors increases by improving the performance and functionality of adders. Carry look-ahead (CLA) adder’s principle remains dominant in High-speed adder architectures, so the carry delay can be improved by calculating each stage in parallel. In this paper by using an 4-bit Manchester carry chain (MCC) adder block in multi output domino CMOS logic. The even and odd carries of this adder are computed in parallel by two independent 2-bit carry chains. Implementation of wider adders based on the use of 4-bit adder module improves the operating speed compared to adders based on the standard 4-bit MCC adder module. Proposed design technique can be used for the implementation of 4, 8, 16 and 32 bit adders in multi output domino logic by using mentor graphics

LOW-POWER SELECTIVE PATTERN COMPRESSION TECHNIQUES IN DIGITAL VLSI CIRCUITS

In this paper, we discuss a productive test-autonomous pressure method for concurrent decrease of test data volume and test power for sweep based test applications. The pre-created test sets acquired from ATPG device are separated into two gatherings in view of the quantity of unspecified bits in every test set. Test pressure system is connected just to the gathering of test sets which contain more unspecified bits and the power decrease strategy is connected to the rest of the test sets. In the proposed approach, the unspecified bits in the pre-produced test sets are specifically mapped with 0s or 1s in view of their viability in diminishing the test data volume and power consumptions. We additionally display a basic decoder design for on-chip decompression. Exploratory results on ISCAS'89 benchmark circuits show the viability of the proposed procedure contrasted and other test-free pressure systems

LOW POWER TEST DATA COMPRESSION AND POWER MINIMIZATION METHODS FOR DIGITAL VLSI CIRCUITS

The measure of data required to test ICs are expanding quickly with the improvements of innovation. Likewise, outline of low-power superior compact registering gadgets has turned into a noteworthy target for the outline engineers. Notwithstanding, diminishment of power scattering is a basic parameter for configuration engineers, as well as for DFT builds as the framework devour considerably more power amid test than amid ordinary operation. In this way, low-power test data pressure for digital VLSI frameworks has turned into a noteworthy sympathy toward specialists and researchers of these ranges as of late. Because of the expansion in the test data volume and high test power, this range has dependably been effectively looked into on and various test data pressure and power decrease methods are presented. This part audits the significant test data pressure and power minimization systems proposed in the writing

HIGH-SPEED MULTIOUTPUT CLA-ADDERS USING 8-BIT MCC ADDER IN DOMINO LOGIC

Adders are the critical parts of processor circuits. The performance of processors increases by improving the performance and functionality of adders. Carry look-ahead (CLA) adder’s principle remains dominant in High-speed adder architectures, so the carry delay can be improved by calculating each stage in parallel. In this project by using an 8-bit Manchester carry chain (MCC) adder block in multi output domino CMOS logic. The even and odd carries of this adder are computed in parallel by two independent 4-bit carry chains. Implementation of wider adders based on the use of 8-bit adder module improves the operating speed compared to adders based on the standard 4-bit MCC adder module. Proposed design technique can be used for the implementation of 8, 16, 32 and 64 bit adders in multi output domino logic by using mentor graphics

Synthesis and Biological Activity of Some new 2-Heterocyclic/acyclic amino/4&apos;-acetamidophenoxy-3- (4-chloro-phenyl)-3, 4-dihydrobenzo[e]- [1,3,2]oxazaphosphinine 2-sulfides

Abstract: 2-Heterocyclic/acyclicamino/4&apos;-acetamidophenoxy-3-(4-chlorophenyl)-3,4-dihydrobenzo-[e][1,3,2]oxazaphosphinine 2-sulfides (4a-j) were synthesized through a two steps process. In the first step, 2-chloro-3-(4-chlorophenyl)-3, 4-dihydrobenzo[e] [1,3,2]-oxazaphosphinine 2-sulfide (2) was prepared by the reaction of 2-[(4-chlorophenylamino)methyl]phenol (1) with thiophosphoryl chloride in the presence of triethylamine in dry toluene-tetrahydrofuran. In the second step, 2 was treated with various heterocyclic/acyclicamines/4&apos;-acetamidophenol in presence of triethylamine-/sodium hydride in toluenetetrahydrofuran at 45-50°C. All the synthesized compounds (4a-j) were characterized by elemental analysis, IR, NMR ( 1 H, 13 C and 31 P) and mass spectra and their biological activity was evaluated for antimicrobial activity

Deficient expression of DNA repair enzymes in early progression to sporadic colon cancer

BACKGROUND:Cancers often arise within an area of cells (e.g. an epithelial patch) that is predisposed to the development of cancer, i.e. a "field of cancerization" or "field defect." Sporadic colon cancer is characterized by an elevated mutation rate and genomic instability. If a field defect were deficient in DNA repair, DNA damages would tend to escape repair and give rise to carcinogenic mutations.PURPOSE:To determine whether reduced expression of DNA repair proteins Pms2, Ercc1 and Xpf (pairing partner of Ercc1) are early steps in progression to colon cancer.RESULTS:Tissue biopsies were taken during colonoscopies of 77 patients at 4 different risk levels for colon cancer, including 19 patients who had never had colonic neoplasia (who served as controls). In addition, 158 tissue samples were taken from tissues near or within colon cancers removed by resection and 16 tissue samples were taken near tubulovillous adenomas (TVAs) removed by resection. 568 triplicate tissue sections (a total of 1,704 tissue sections) from these tissue samples were evaluated by immunohistochemistry for 4 DNA repair proteins. Substantially reduced protein expression of Pms2, Ercc1 and Xpf occurred in field defects of up to 10 cm longitudinally distant from colon cancers or TVAs and within colon cancers. Expression of another DNA repair protein, Ku86, was infrequently reduced in these areas. When Pms2, Ercc1 or Xpf were reduced in protein expression, then either one or both of the other two proteins most often had reduced protein expression as well. The mean inner colon circumferences, from 32 resections, of the ascending, transverse and descending/sigmoid areas were measured as 6.6 cm, 5.8 cm and 6.3 cm, respectively. When combined with other measurements in the literature, this indicates the approximate mean number of colonic crypts in humans is 10 million.CONCLUSIONS:The substantial deficiencies in protein expression of DNA repair proteins Pms2, Ercc1 and Xpf in about 1 million crypts near cancers and TVAs suggests that the tumors arose in field defects that were deficient in DNA repair and that deficiencies in Pms2, Ercc1 and Xpf are early steps, often occurring together, in progression to colon cancer.This item is part of the UA Faculty Publications collection. For more information this item or other items in the UA Campus Repository, contact the University of Arizona Libraries at [email protected]