Mal-Who? Mal-What? Mal-Where? The Future Cyber-Threat Of A Non-Fiction Neuromancer: Legally Un-Attributable, Cyberspace-Bound, Decentralized Autonomous Entities

For decades, science fiction writers have tackled philosophical and existential questions arising from the creation of artificial intelligence (“AI”) by human beings. AI, however, is no longer a fictional concept, but rather an evolving part of modern society. How will AI systems impact United States’ national security interests? Considering the increased national security threat coming from actors in cyberspace, policymakers should consider the cybersecurity risk of AI systems that operate entirely in cyberspace. This article opines that a serious threat to national security will arise from a cyberspace-bound, decentralized autonomous entity (“CyDAE”) because of the “unexplainability” of current AI system design (that is, the difficulty understanding why or how the AI arrived at its conclusion or behaved the way it did), the lack of legal personhood arrangements for autonomous systems, and the already difficult task of attributing acts in cyberspace to human actors or States because of outdated Westphalian notions of sovereignty and territoriality. The article ultimately offers several broad policy suggestions, including: (1) an AI registry; (2) “explainability” criteria for AI system designs; (3) requiring human oversight for legal personhood arrangements (whether arranged in a corporation, limited liability structure, or otherwise) tailored specifically for AI autonomous systems that lack human members; and (4) universal jurisdiction of States over malicious CyDAEs that obfuscate attributive links to human actors or States

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results

Insights Into Global Engineering Education After the Birth of Industry 5.0

Insights Into Global Engineering Education After the Birth of Industry 5.0 presents a comprehensive overview of recent developments in the fields of engineering and technology. The book comprises single chapters authored by various researchers and edited by an expert active in the engineering education research area. It provides a thorough overview of the latest research efforts by international authors on engineering education and opens potential new research paths for further novel developments

Techniques for Improving Security and Trustworthiness of Integrated Circuits

The integrated circuit (IC) development process is becoming increasingly vulnerable to malicious activities because untrusted parties could be involved in this IC development flow. There are four typical problems that impact the security and trustworthiness of ICs used in military, financial, transportation, or other critical systems: (i) Malicious inclusions and alterations, known as hardware Trojans, can be inserted into a design by modifying the design during GDSII development and fabrication. Hardware Trojans in ICs may cause malfunctions, lower the reliability of ICs, leak confidential information to adversaries or even destroy the system under specifically designed conditions. (ii) The number of circuit-related counterfeiting incidents reported by component manufacturers has increased significantly over the past few years with recycled ICs contributing the largest percentage of the total reported counterfeiting incidents. Since these recycled ICs have been used in the field before, the performance and reliability of such ICs has been degraded by aging effects and harsh recycling process. (iii) Reverse engineering (RE) is process of extracting a circuit’s gate-level netlist, and/or inferring its functionality. The RE causes threats to the design because attackers can steal and pirate a design (IP piracy), identify the device technology, or facilitate other hardware attacks. (iv) Traditional tools for uniquely identifying devices are vulnerable to non-invasive or invasive physical attacks. Securing the ID/key is of utmost importance since leakage of even a single device ID/key could be exploited by an adversary to hack other devices or produce pirated devices. In this work, we have developed a series of design and test methodologies to deal with these four challenging issues and thus enhance the security, trustworthiness and reliability of ICs. The techniques proposed in this thesis include: a path delay fingerprinting technique for detection of hardware Trojans, recycled ICs, and other types counterfeit ICs including remarked, overproduced, and cloned ICs with their unique identifiers; a Built-In Self-Authentication (BISA) technique to prevent hardware Trojan insertions by untrusted fabrication facilities; an efficient and secure split manufacturing via Obfuscated Built-In Self-Authentication (OBISA) technique to prevent reverse engineering by untrusted fabrication facilities; and a novel bit selection approach for obtaining the most reliable bits for SRAM-based physical unclonable function (PUF) across environmental conditions and silicon aging effects

Stiffening of deployable space booms: Automated Protein Crystal Growth Facility

Part of the curriculum for the seniors at Vanderbilt University in the Mechanical Engineering Program is to take a design class. The purpose of the class is to expose the students to the open ended problems which working engineers are involved with every day. In the past, the students have been asked to work in a variety of projects developed by the professor. This year Vanderbilt was admitted into the Advanced Design Program (ADP) sponsored by the Universities Space Research Association (USRA) and the National Aeronautics and Space Association (NASA). The grant sponsored undergraduate design and research into new and innovative areas in which NASA is involved. The grant sponsors the Teaching Assistant as well as provides monies for travel and other expenses. The design and research of the seniors of the 1992-1993 school year in association with NASA and USRA is documented

Design and performance optimization of asynchronous networks-on-chip

As digital systems continue to grow in complexity, the design of conventional synchronous systems is facing unprecedented challenges. The number of transistors on individual chips is already in the multi-billion range, and a greatly increasing number of components are being integrated onto a single chip. As a consequence, modern digital designs are under strong time-to-market pressure, and there is a critical need for composable design approaches for large complex systems. In the past two decades, networks-on-chip (NoC’s) have been a highly active research area. In a NoC-based system, functional blocks are first designed individually and may run at different clock rates. These modules are then connected through a structured network for on-chip global communication. However, due to the rigidity of centrally-clocked NoC’s, there have been bottlenecks of system scalability, energy and performance, which cannot be easily solved with synchronous approaches. As a result, there has been significant recent interest in combing the notion of asynchrony with NoC designs. Since the NoC approach inherently separates the communication infrastructure, and its timing, from computational elements, it is a natural match for an asynchronous paradigm. Asynchronous NoC’s, therefore, enable a modular and extensible system composition for an ‘object-orient’ design style. The thesis aims to significantly advance the state-of-art and viability of asynchronous and globally-asynchronous locally-synchronous (GALS) networks-on-chip, to enable high-performance and low-energy systems. The proposed asynchronous NoC’s are nearly entirely based on standard cells, which eases their integration into industrial design flows. The contributions are instantiated in three different directions. First, practical acceleration techniques are proposed for optimizing the system latency, in order to break through the latency bottleneck in the memory interfaces of many on-chip parallel processors. Novel asynchronous network protocols are proposed, along with concrete NoC designs. A new concept, called ‘monitoring network’, is introduced. Monitoring networks are lightweight shadow networks used for fast-forwarding anticipated traffic information, ahead of the actual packet traffic. The routers are therefore allowed to initiate and perform arbitration and channel allocation in advance. The technique is successfully applied to two topologies which belong to two different categories – a variant mesh-of-trees (MoT) structure and a 2D-mesh topology. Considerable and stable latency improvements are observed across a wide range of traffic patterns, along with moderate throughput gains. Second, for the first time, a high-performance and low-power asynchronous NoC router is compared directly to a leading commercial synchronous counterpart in an advanced industrial technology. The asynchronous router design shows significant performance improvements, as well as area and power savings. The proposed asynchronous router integrates several advanced techniques, including a low-latency circular FIFO for buffer design, and a novel end-to-end credit-based virtual channel (VC) flow control. In addition, a semi-automated design flow is created, which uses portions of a standard synchronous tool flow. Finally, a high-performance multi-resource asynchronous arbiter design is developed. This small but important component can be directly used in existing asynchronous NoC’s for performance optimization. In addition, this standalone design promises use in opening up new NoC directions, as well as for general use in parallel systems. In the proposed arbiter design, the allocation of a resource to a client is divided into several steps. Multiple successive client-resource pairs can be selected rapidly in pipelined sequence, and the completion of the assignments can overlap in parallel. In sum, the thesis provides a set of advanced design solutions for performance optimization of asynchronous and GALS networks-on-chip. These solutions are at different levels, from network protocols, down to router- and component-level optimizations, which can be directly applied to existing basic asynchronous NoC designs to provide a leap in performance improvement

Formal Power Analysis of Systems-on-Chip

The design methods and languages targeted to modern System-on-Chip designs are facing tremendous pressure of the ever-increasing complexity, power, and speed requirements. To estimate any of these three metrics, there is a trade-off between accuracy and abstraction level of detail in which a system under design is analyzed. The more detailed the description, the more accurate the simulation will be, but, on the other hand, the more time consuming it will be. Moreover, a designer wants to make decisions as early as possible in the design flow to avoid costly design backtracking. To answer the challenges posed upon System-on-chip designs, this thesis introduces a formal, power aware framework, its development methods, and methods to constraint and analyze power consumption of the system under design. This thesis discusses on power analysis of synchronous and asynchronous systems not forgetting the communication aspects of these systems. The presented framework is built upon the Timed Action System formalism, which offer an environment to analyze and constraint the functional and temporal behavior of the system at high abstraction level. Furthermore, due to the complexity of System-on-Chip designs, the possibility to abstract unnecessary implementation details at higher abstraction levels is an essential part of the introduced design framework. With the encapsulation and abstraction techniques incorporated with the procedure based communication allows a designer to use the presented power aware framework in modeling these large scale systems. The introduced techniques also enable one to subdivide the development of communication and computation into own tasks. This property is taken into account in the power analysis part as well. Furthermore, the presented framework is developed in a way that it can be used throughout the design project. In other words, a designer is able to model and analyze systems from an abstract specification down to an implementable specification.Siirretty Doriast

NASA Tech Briefs, April 1997

Topics covered include: Video and Imaging; Electronic Components and Circuits; Electronic Systems; Physical Sciences; Materials; Computer Programs; Mechanics; Machinery/Automation; Manufacturing/Fabrication; Mathematics and Information Sciences; Life Sciences; Books and Reports

Riverine sustainment 2012

Student Integrated ProjectIncludes supplementary materialThis technical report analyzed the Navy's proposed Riverine Force (RF) structure and capabilities for 2012. The Riverine Sustainment 2012 Team (RST) examined the cost and performance of systems of systems which increased RF sustainment in logistically barren environments. RF sustainment was decomposed into its functional areas of supply, repair, and force protection. The functional and physical architectures were developed in parallel and were used to construct an operational architecture for the RF. The RST used mathematical, agent-based and queuing models to analyze various supply, repair and force protection system alternatives. Extraction of modeling data revealed several key insights. Waterborne heavy lift connectors such as the LCU-2000 are vital in the re-supply of the RF when it is operating up river in a non-permissive environment. Airborne heavy lift connectors such as the MV-22 were ineffective and dominated by the waterborne variants in the same environment. Increase in manpower and facilities did appreciable add to the operational availability of the RF. Mean supply response time was the biggest factor effecting operational availability and should be kept below 24 hours to maintain operational availability rates above 80%. Current mortar defenses proposed by the RF are insufficient.N