1,890 research outputs found

    Exact performance analysis of a single-wavelength optical buffer with correlated inter-arrival times

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    Providing a photonic alternative to the current electronic switching in the backbone, optical packet switching (OPS) and optical bursts witching (OBS) require optical buffering. Optical buffering exploits delays in long optical fibers; an optical buffer is implemented by routing packets through a set of fiber delay lines (FDLs). Previous studies pointed out that, in comparison with electronic buffers, optical buffering suffers from an additional performance degradation. This contribution builds on this observation by studying optical buffer performance under more general traffic assumptions. Features of the optical buffer model under consideration include a Markovian arrival process, general burst sizes and a finite set of fiber delay lines of arbitrary length. Our algorithmic approach yields instant analytic results for important performance measures such as the burst loss ratio and the mean delay

    Architecture, design, and modeling of the OPSnet asynchronous optical packet switching node

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    An all-optical packet-switched network supporting multiple services represents a long-term goal for network operators and service providers alike. The EPSRC-funded OPSnet project partnership addresses this issue from device through to network architecture perspectives with the key objective of the design, development, and demonstration of a fully operational asynchronous optical packet switch (OPS) suitable for 100 Gb/s dense-wavelength-division multiplexing (DWDM) operation. The OPS is built around a novel buffer and control architecture that has been shown to be highly flexible and to offer the promise of fair and consistent packet delivery at high load conditions with full support for quality of service (QoS) based on differentiated services over generalized multiprotocol label switching

    Optical Networks for Future Internet Design

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    Node design in optical packet switched networks

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    Resource allocation and scalability in dynamic wavelength-routed optical networks.

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    This thesis investigates the potential benefits of dynamic operation of wavelength-routed optical networks (WRONs) compared to the static approach. It is widely believed that dynamic operation of WRONs would overcome the inefficiencies of the static allocation in improving resource use. By rapidly allocating resources only when and where required, dynamic networks could potentially provide the same service that static networks but at decreased cost, very attractive to network operators. This hypothesis, however, has not been verified. It is therefore the focus of this thesis to investigate whether dynamic operation of WRONs can save significant number of wavelengths compared to the static approach whilst maintaining acceptable levels of delay and scalability. Firstly, the wavelength-routed optical-burst-switching (WR-OBS) network architecture is selected as the dynamic architecture to be studied, due to its feasibility of implementation and its improved network performance. Then, the wavelength requirements of dynamic WR-OBS are evaluated by means of novel analysis and simulation and compared to that of static networks for uniform and non-uniform traffic demand. It is shown that dynamic WR-OBS saves wavelengths with respect to the static approach only at low loads and especially for sparsely connected networks and that wavelength conversion is a key capability to significantly increase the benefits of dynamic operation. The mean delay introduced by dynamic operation of WR-OBS is then assessed. The results show that the extra delay is not significant as to violate end-to-end limits of time-sensitive applications. Finally, the limiting scalability of WR-OBS as a function of the lightpath allocation algorithm computational complexity is studied. The trade-off between the request processing time and blocking probability is investigated and a new low-blocking and scalable lightpath allocation algorithm which improves the mentioned trade-off is proposed. The presented algorithms and results can be used in the analysis and design of dynamic WRONs

    Packet Loss Rate Differentiation in slotted Optical Packet Switching OCDM/WDM

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    We propose a multi-class mechanism for Optical Code Division Multiplexing (OCDM), Wavelength Division Multiplexing (WDM) Optical Packet Switch (OPS) architecture capable of supporting Quality of Service (QoS) transmission. OCDM/WDM has been proposed as a competitive hybrid switching technology to support the next generation optical Internet. This paper addresses performance issues in the slotted OPS networks and proposed four differentiation schemes to support Quality of Service. In addition, we present a comparison between the proposed schemes as well as, a simulation scheduler design which can be suitable for the core switch node in OPS networks. Using software simulations the performance of our algorithm in terms of losing probability, the packet delay, and scalability is evaluated

    Control Plane Hardware Design for Optical Packet Switched Data Centre Networks

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    Optical packet switching for intra-data centre networks is key to addressing traffic requirements. Photonic integration and wavelength division multiplexing (WDM) can overcome bandwidth limits in switching systems. A promising technology to build a nanosecond-reconfigurable photonic-integrated switch, compatible with WDM, is the semiconductor optical amplifier (SOA). SOAs are typically used as gating elements in a broadcast-and-select (B\&S) configuration, to build an optical crossbar switch. For larger-size switching, a three-stage Clos network, based on crossbar nodes, is a viable architecture. However, the design of the switch control plane, is one of the barriers to packet switching; it should run on packet timescales, which becomes increasingly challenging as line rates get higher. The scheduler, used for the allocation of switch paths, limits control clock speed. To this end, the research contribution was the design of highly parallel hardware schedulers for crossbar and Clos network switches. On a field-programmable gate array (FPGA), the minimum scheduler clock period achieved was 5.0~ns and 5.4~ns, for a 32-port crossbar and Clos switch, respectively. By using parallel path allocation modules, one per Clos node, a minimum clock period of 7.0~ns was achieved, for a 256-port switch. For scheduler application-specific integrated circuit (ASIC) synthesis, this reduces to 2.0~ns; a record result enabling scalable packet switching. Furthermore, the control plane was demonstrated experimentally. Moreover, a cycle-accurate network emulator was developed to evaluate switch performance. Results showed a switch saturation throughput at a traffic load 60\% of capacity, with sub-microsecond packet latency, for a 256-port Clos switch, outperforming state-of-the-art optical packet switches
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