Network Electrophysiology Sensor-On-A- Chip

Electroencephalogram (EEG), Electrocardiogram (ECG), and Electromyogram (EMG) bio-potential signals are commonly recorded in clinical practice. Typically, patients are connected to a bulky and mains-powered instrument, which reduces their mobility and creates discomfort. This limits the acquisition time, prevents the continuous monitoring of patients, and can affect the diagnosis of illness. Therefore, there is a great demand for low-power, small-size, and ambulatory bio-potential signal acquisition systems. Recent work on instrumentation amplifier design for bio-potential signals can be broadly classified as using one or both of two popular techniques: In the first, an AC-coupled signal path with a MOS-Bipolar pseudo resistor is used to obtain a low-frequency cutoff that passes the signal of interest while rejecting large dc offsets. In the second, a chopper stabilization technique is designed to reduce 1/f noise at low frequencies. However, both of these existing techniques lack control of low-frequency cutoff. This thesis presents the design of a mixed- signal integrated circuit (IC) prototype to provide complete, programmable analog signal conditioning and analog-to-digital conversion of an electrophysiologic signal. A front-end amplifier is designed with low input referred noise of 1 uVrms, and common mode rejection ratio 102 dB. A novel second order sigma-delta analog- to-digital converter (ADC) with a feedback integrator from the sigma-delta output is presented to program the low-frequency cutoff, and to enable wide input common mode range of ¡Ãƒâ€œ0.3 V. The overall system is implemented in Jazz Semiconductor 0.18 um CMOS technology with power consumption 5.8 mW from ¡Ãƒâ€œ0.9V power supplies

Digital Filters

The new technology advances provide that a great number of system signals can be easily measured with a low cost. The main problem is that usually only a fraction of the signal is useful for different purposes, for example maintenance, DVD-recorders, computers, electric/electronic circuits, econometric, optimization, etc. Digital filters are the most versatile, practical and effective methods for extracting the information necessary from the signal. They can be dynamic, so they can be automatically or manually adjusted to the external and internal conditions. Presented in this book are the most advanced digital filters including different case studies and the most relevant literature

TESTING OF RECURSIVE AND NON-RECURSIVE ALGORITHMS FOR REAL-TIME PHASOR AND FREQUENCY ESTIMATIONS IN POWER SYSTEMS

Steady-state performance of various recursive and non-recursive algorithms are tested in this report according to the test signals given in the IEEE Standard C37.118.1-2011. Phase magnitude and phase angle of the power grid signals have been estimated using Discrete Fourier Transform (non-recursive), Discrete Fourier Transform (recursive), Least Square, and Wavelet Transform Algorithms. Frequency estimation is performed using Discrete Fourier Transform, Weighted Least Square, and Zero Crossing methods. These algorithms are evaluated in LabView software and tested by generating test signals in a Simulink model. Furthermore, Total Vector Error (TVE) is calculated using dynamic test signals as per the IEEE Standard C37.118-2011. Performance of different algorithms are analyzed for various cases and the value of TVE is compared with the permissible error limits given in the standard

A Study into Speech Enhancement Techniques in Adverse Environment

This dissertation developed speech enhancement techniques that improve the speech quality in applications such as mobile communications, teleconferencing and smart loudspeakers. For these applications it is necessary to suppress noise and reverberation. Thus the contribution in this dissertation is twofold: single channel speech enhancement system which exploits the temporal and spectral diversity of the received microphone signal for noise suppression and multi-channel speech enhancement method with the ability to employ spatial diversity to reduce reverberation

Digital Filter Design Using Improved Artificial Bee Colony Algorithms

Digital filters are often used in digital signal processing applications. The design objective of a digital filter is to find the optimal set of filter coefficients, which satisfies the desired specifications of magnitude and group delay responses. Evolutionary algorithms are population-based meta-heuristic algorithms inspired by the biological behaviors of species. Compared to gradient-based optimization algorithms such as steepest descent and Newton’s like methods, these bio-inspired algorithms have the advantages of not getting stuck at local optima and being independent of the starting point in the solution space. The limitations of evolutionary algorithms include the presence of control parameters, problem specific tuning procedure, premature convergence and slower convergence rate. The artificial bee colony (ABC) algorithm is a swarm-based search meta-heuristic algorithm inspired by the foraging behaviors of honey bee colonies, with the benefit of a relatively fewer control parameters. In its original form, the ABC algorithm has certain limitations such as low convergence rate, and insufficient balance between exploration and exploitation in the search equations. In this dissertation, an ABC-AMR algorithm is proposed by incorporating an adaptive modification rate (AMR) into the original ABC algorithm to increase convergence rate by adjusting the balance between exploration and exploitation in the search equations through an adaptive determination of the number of parameters to be updated in every iteration. A constrained ABC-AMR algorithm is also developed for solving constrained optimization problems.There are many real-world problems requiring simultaneous optimizations of more than one conflicting objectives. Multiobjective (MO) optimization produces a set of feasible solutions called the Pareto front instead of a single optimum solution. For multiobjective optimization, if a decision maker’s preferences can be incorporated during the optimization process, the search process can be confined to the region of interest instead of searching the entire region. In this dissertation, two algorithms are developed for such incorporation. The first one is a reference-point-based MOABC algorithm in which a decision maker’s preferences are included in the optimization process as the reference point. The second one is a physical-programming-based MOABC algorithm in which physical programming is used for setting the region of interest of a decision maker. In this dissertation, the four developed algorithms are applied to solve digital filter design problems. The ABC-AMR algorithm is used to design Types 3 and 4 linear phase FIR differentiators, and the results are compared to those obtained by the original ABC algorithm, three improved ABC algorithms, and the Parks-McClellan algorithm. The constrained ABC-AMR algorithm is applied to the design of sparse Type 1 linear phase FIR filters of filter orders 60, 70 and 80, and the results are compared to three state-of-the-art design methods. The reference-point-based multiobjective ABC algorithm is used to design of asymmetric lowpass, highpass, bandpass and bandstop FIR filters, and the results are compared to those obtained by the preference-based multiobjective differential evolution algorithm. The physical-programming-based multiobjective ABC algorithm is used to design IIR lowpass, highpass and bandpass filters, and the results are compared to three state-of-the-art design methods. Based on the obtained design results, the four design algorithms are shown to be competitive as compared to the state-of-the-art design methods

NONUNIFORMLY SAMPLED DIGITAL SIGNAL PROCESSING FOR LOW-POWER BIOMEDICAL APPLICATIONS.

Ph.DDOCTOR OF PHILOSOPH

Digital Filters and Signal Processing

Digital filters, together with signal processing, are being employed in the new technologies and information systems, and are implemented in different areas and applications. Digital filters and signal processing are used with no costs and they can be adapted to different cases with great flexibility and reliability. This book presents advanced developments in digital filters and signal process methods covering different cases studies. They present the main essence of the subject, with the principal approaches to the most recent mathematical models that are being employed worldwide

Impact of prominent synchrophasor estimation algorithms on power system stability assessment

The electricity network is a critical infrastructure and its reliability is of paramount importance for the functionality of many critical systems in the modern society. Power system stability is one of the imperative aspects that impacts the reliability of electrical networks, hence power system stability needs to be observed in real-time for secure and reliable operation of the power grids. Conventionally, supervisory control and data acquisition (SCADA) based wide-area monitoring systems (WAMS) have been used for this purpose, however, they are predominantly designed to detect static changes in steady-state stability. In contrast, modern wide-area power networks pose significant challenges such as presence of power electronic switching loads and inductive motor loads, asynchronous distributed generation and dynamic fluctuations in demand and supply. Synchrophasor based WAMS is the next generation WAMS technology and offers great advantages over traditional SCADA systems such as precise time synchronisation, universally accepted standardisation and extremely fast and robust phasor estimation. A strategically placed network of phasor measurement units (PMUs) enables full visibility of the entire power network. Time synchronised PMU data can then be transferred to a phasor data centre (PDC) using efficient communication algorithms where multi facet analysis, including realtime stability assessment, could be performed. Despite significant benefits of the synchrophasor technology, several factors have hindered the widespread adoption ofthe synchrophasor technology. This research addresses such contemporary issues. The first phase of this research details an empirical study of existing synchrophasor estimation algorithms (SEAs) and considers the need for a benchmark in terms of robustness. Synchrophasor research is heavily populated with studies presenting diverse SEAs. Interestingly, not many studies have attempted to develop a robust SEA based on the mathematical technique proposed in the original Institute of Electrical and Electronics Engineers (IEEE) standardisation (i.e. IEEE std. C37.118.1-2011), the quadrature demodulation (QD) technique. Therefore, a verifiable benchmark algorithm is not currently available. This research presents comprehensive synchrophasor estimation models developed based on the QD technique and is then presented as the benchmark SEA. Proposed models are tested against all compliance requirements stipulated in the latest IEEE standardisation. Furthermore, a detailed comparison of prominent synchrophasor models is conducted against the proposed benchmark models, to understand the impact of the SEAs on the overall phasor estimation. Results establish a clear link between the accuracy/latency of the phasor estimation and the accompanying synchrophasor algorithm. The second phase of this research involves testing and comparison of synchrophasor models on hardware platforms. Even though development of SEA has been a prominent research area, only a few of these studies have been verified and validated with field tested results. This is a significant barrier to the advent of improved SEAs beyond academic literature, especially in industrial applications. A laboratory scale, hardware based synchrophasor test platform is proposed where any synchrophasor algorithm can be tested for any test condition or fault signal. Key highlights of this section include; global position system (GPS) time synchronisation of synchrophasors and a sinusoidal pulse width modulation (SPWM) technique based scalable input system capable of generating measurement conditions emulating any fault condition. Results establish the superiority of the proposed benchmark algorithm and identify key implementation issues in hardware implementation of some of the prominent synchrophasor models. The final phase of this research develops a synchrophasor based WAMS by using a bottom-up approach to evaluate real-time stability of wide-area networks under practical power network fault conditions. As part of this research the analyses and the impact of SEAs on the overall stability assessment has been evaluated. Development and testing of PMUs, and stability studies are historically conducted in two disjointed silos. As a result, stability analysis is often conducted based on the assumption that the PMU data delivered to the PDC are accurate and instantaneous. On the other hand, SEAs are tested against the compliance criteria listed in the IEEE standardisation which do not involve any practical power network faults. This study attempts to dive into this unexplored territory. Performance in realtime voltage and frequency stability of prominent SEAs is evaluated by employing a strategically placed PMU network on two standard power networks simulation models. The IEEE 9-bus system and New England 39-bus system are considered and consists synchronous generation sources, dynamic load centres and transmission links. By modelling practical transient fault conditions such as short circuit faults, loss of generation and addition of load centres, the real-time voltage and frequency stability have been studied. A modified highest Lyapunov exponent (HLE) based real-time stability assessment algorithm (RSAA) is proposed to suit implementation in practical power networks. Despite the full compliance against the IEEE standardisation, tested algorithms produce significantly different outcomes in the stability assessment that may directly impact on the subsequent activation of protection systems and overall network stability. Results of this study point to interesting findings and establishes a clear link between the reliability and the performance of the underlining SEA. In conclusion, key findings of this research contribute to two prominent areas within the synchrophasor research; SEA development and testing, and real-time stability assessment. This research has established a strong link between these disjointed research fields, thereby enabling future advancements synchrophasor based stability monitoring and control systems

Power System Transients: Impacts of Non-Ideal Sensors on Measurement-Based Applications

The power system is comprised of thousands of lines, generation sources, transformers, and other equipment responsible for servicing millions of customers. Such a complex apparatus requires constant monitoring and protection schemes capable of keeping the system operational, reliable, and resilient. To achieve these goals, measurement is a critical role in the continued functionality of the power system. However, measurement devices are never completely reliable, and are susceptible to inherent irregularities; imparting potentially misleading distortions on measurements containing high-frequency components. This dissertation analyzes some of these effects, as well as the way they may impact certain applications in the grid that utilize these kinds of measurements. This dissertation first presents background on existing measurement technologies currently in use in the power grid, with extra emphasis placed on point-on-wave (PoW) sensors, those designed to capture oscillographic records of voltage and current signals. Next, a waveform “playback” system, developed at Oak Ridge National Laboratory’s Distributed Energy Communications \& Control (DECC) laboratory was used for comparisons between various line-post-monitor PoW sensors when subjected to different high-frequency current disturbances. Each of the three sensors exhibited unique quirks in these spectral regions, both in terms of harmonic magnitude and phase angle. A goodness-of-fit metric for comparing an ideal reference sensor with the test sensors was adopted from the literature and showed the extremes to which two test sensors vastly under performed when compared to the third. The subsequent chapter analyzes these behaviors under a statistical lens, using kernel density estimation to fit probability density functions (PDFs) to error distributions at specific harmonic frequencies resulting from sensor frequency response distortions. The remaining two chapters of the dissertation are concerned with resultant effects on applications that require high-frequency transient data. First, a detection algorithm is presented, and its performance when subjected to statistical errors inherent in these sensors is quantified. The dissertation culminates with a study on an artificial intelligence (AI) technique for estimating the location of capacitor switching transients, as well as learning prediction intervals that indicate the level of uncertainty present in the data caused by sensor frequency response irregularities

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling proved to effectively reduce the energy consumption of digital circuits, additional energy savings are still required for a longer battery life. One of the main limitations of essentially any low-energy technique is the potential degradation of the quality of service (QoS). Thus, a thorough understanding of how circuits behave when operated around the point of first failure (PoFF) is key for the effective application of conventional energy-efficient methods as well as for the development of future low-energy techniques. In this thesis, a variety of circuits, techniques, and tools is described to reduce the energy consumption in digital systems when operated either in the safe and conservative exact region, close to the PoFF, or even inside the inexact region. A straightforward approach to reduce the power consumed by clock distribution while safely operating in the exact region is dual-edge-triggered (DET) clocking. However, the DET approach is rarely taken, primarily due to the perceived complexity of its integration. In this thesis, a fully automated design flow is introduced for applying DET clocking to a conventional single-edge-triggered (SET) design. In addition, the first static true-single-phase-clock DET flip-flop (DET-FF) that completely avoids clock-overlap hazards of DET registers is proposed. Even though the correct timing of synchronous circuits is ensured in worst-case conditions, the critical path might not always be excited. Thus, dynamic clock adjustment (DCA) has been proposed to trim any available dynamic timing margin by changing the operating clock frequency at runtime. This thesis describes a dynamically-adjustable clock generator (DCG) capable of modifying the period of the produced clock signal on a cycle-by-cycle basis that enables the DCA technique. In addition, a timing-monitoring sequential (TMS) that detects input transitions on either one of the clock phases to enable the selection of the best timing-monitoring strategy at runtime is proposed. Energy-quality scaling techniques aimat trading lower energy consumption for a small degradation on the QoS whenever approximations can be tolerated. In this thesis, a low-power methodology for the perturbation of baseline coefficients in reconfigurable finite impulse response (FIR) filters is proposed. The baseline coefficients are optimized to reduce the switching activity of the multipliers in the FIR filter, enabling the possibility of scaling the power consumption of the filter at runtime. The area as well as the leakage power of many system-on-chips is often dominated by embedded memories. Gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to the conventional static random-access memory (SRAM) when a higher memory density is desired. However, due to GC-eDRAMs relying on many interdependent variables, the adaptation of existing memories and the design of future GCeDRAMs prove to be highly complex tasks. Thus, the first modeling tool that estimates timing, memory availability, bandwidth, and area of GC-eDRAMs for a fast exploration of their design space is proposed in this thesis