Voltage island-driven floorplanning.

Ma, Qiang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2008.Includes bibliographical references (leaves 78-80).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Floorplanning --- p.2Chapter 1.3 --- Motivations --- p.4Chapter 1.4 --- Design Implementation of Voltage Islands --- p.5Chapter 1.5 --- Problem Formulation --- p.8Chapter 1.6 --- Progress on the Problem --- p.10Chapter 1.7 --- Contributions --- p.12Chapter 1.8 --- Thesis Organization --- p.14Chapter 2 --- Literature Review on MSV --- p.15Chapter 2.1 --- Introduction --- p.15Chapter 2.2 --- MSV at Post-floorplan/Post Placement Stage --- p.16Chapter 2.2.1 --- """Post-Placement Voltage Island Generation under Performance Requirement""" --- p.16Chapter 2.2.2 --- """Post-Placement Voltage Island Generation""" --- p.18Chapter 2.2.3 --- """Timing-Constrained and Voltage-Island-Aware Voltage Assignment""" --- p.19Chapter 2.2.4 --- """Voltage Island Generation under Performance Requirement for SoC Designs""" --- p.20Chapter 2.2.5 --- """An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning""" --- p.21Chapter 2.3 --- MSV at Floorplan/Placement Stage --- p.22Chapter 2.3.1 --- """Architecting Voltage Islands in Core-based System-on-a- Chip Designs""" --- p.22Chapter 2.3.2 --- """Voltage Island Aware Floorplanning for Power and Timing Optimization""" --- p.23Chapter 2.4 --- Summary --- p.27Chapter 3 --- MSV Driven Floorplanning --- p.29Chapter 3.1 --- Introduction --- p.29Chapter 3.2 --- Problem Formulation --- p.32Chapter 3.3 --- Algorithm Overview --- p.33Chapter 3.4 --- Optimal Island Partitioning and Voltage Assignment --- p.33Chapter 3.4.1 --- Voltage Islands in Non-subtrees --- p.35Chapter 3.4.2 --- Proof of Optimality --- p.36Chapter 3.4.3 --- Handling Island with Power Down Mode --- p.37Chapter 3.4.4 --- Speedup in Implementation and Complexity --- p.38Chapter 3.4.5 --- Varying Background Chip-level Voltage --- p.39Chapter 3.5 --- Simulated Annealing --- p.39Chapter 3.5.1 --- Moves --- p.39Chapter 3.5.2 --- Cost Function --- p.40Chapter 3.6 --- Experimental Results --- p.40Chapter 3.6.1 --- Extension to Minimize Level Shifters --- p.45Chapter 3.6.2 --- Extension to Consider Power Network Routing --- p.46Chapter 3.7 --- Summary --- p.46Chapter 4 --- MSV Driven Floorplanning with Timing --- p.49Chapter 4.1 --- Introduction --- p.49Chapter 4.2 --- Problem Formulation --- p.52Chapter 4.3 --- Algorithm Overview --- p.56Chapter 4.4 --- Voltage Assignment Problem --- p.56Chapter 4.4.1 --- Lagrangian Relaxation --- p.58Chapter 4.4.2 --- Transformation into the Primal Minimum Cost Flow Problem --- p.60Chapter 4.4.3 --- Cost-Scaling Algorithm --- p.64Chapter 4.4.4 --- Solution Transformation --- p.66Chapter 4.5 --- Simulated Annealing --- p.69Chapter 4.5.1 --- Moves --- p.69Chapter 4.5.2 --- Speeding up heuristic --- p.69Chapter 4.5.3 --- Cost Function --- p.70Chapter 4.5.4 --- Annealing Schedule --- p.71Chapter 4.6 --- Experimental Results --- p.71Chapter 4.7 --- Summary --- p.72Chapter 5 --- Conclusion --- p.76Bibliography --- p.8

Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems

Network-on-Chip (NoC) is emerging as a promising communication structure, which is scalable with respect to chip complexity. Meanwhile, latest chip designs are increasingly leveraging multiple voltage-frequency domains for energy-efficiency improvement. In this work, we propose a simultaneous task and voltage scheduling algorithm for energy minimization in NoC based designs. The energy-latency tradeoff is handled by Lagrangian relaxation. The core algorithm is a clustering based approach which not only assigns voltage levels and starting time to each task (or Processing Element) but also naturally finds voltage-frequency clusters. Compared to a recent previous work, which performs task scheduling and voltage assignment sequentially, our method leads to an average of 20 percent energy reduction

PeF: Poisson's Equation Based Large-Scale Fixed-Outline Floorplanning

Floorplanning is the first stage of VLSI physical design. An effective floorplanning engine definitely has positive impact on chip design speed, quality and performance. In this paper, we present a novel mathematical model to characterize non-overlapping of modules, and propose a flat fixed-outline floorplanning algorithm based on the VLSI global placement approach using Poisson's equation. The algorithm consists of global floorplanning and legalization phases. In global floorplanning, we redefine the potential energy of each module based on the novel mathematical model for characterizing non-overlapping of modules and an analytical solution of Poisson's equation. In this scheme, the widths of soft modules appear as variables in the energy function and can be optimized. Moreover, we design a fast approximate computation scheme for partial derivatives of the potential energy. In legalization, based on the defined horizontal and vertical constraint graphs, we eliminate overlaps between modules remained after global floorplanning, by modifying relative positions of modules. Experiments on the MCNC, GSRC, HB+ and ami49\_x benchmarks show that, our algorithm improves the average wirelength by at least 2\% and 5\% on small and large scale benchmarks with certain whitespace, respectively, compared to state-of-the-art floorplanners

Voltage island based heterogeneous NoC design through constraint programming

This paper discusses heterogeneous Network-on-Chip (NoC) design from a Constraint Programming (CP) perspective and extends the formulation to solving Voltage-Frequency Island (VFI) problem. In general, VFI is a superior design alternative in terms of thermal constraints, power consumption as well as performance considerations. Given a Communication Task Graph (CTG) and subsequent task assignments for cores, cores are allocated to the best possible places on the chip in the first stage to minimize the overall communication cost among cores. We then solve the application scheduling problem to determine the optimum core types from a list of technological alternatives and to minimize the makespan. Moreover, an elegant CP model is proposed to solve VFI problem by mapping and grouping cores at the same time with scheduling the computation tasks as a limited capacity resource allocation model. The paper reports results based on real benchmark datasets from the literature. © 2014 Elsevier Ltd. All rights reserved

FPGA dynamic and partial reconfiguration : a survey of architectures, methods, and applications

Dynamic and partial reconfiguration are key differentiating capabilities of field programmable gate arrays (FPGAs). While they have been studied extensively in academic literature, they find limited use in deployed systems. We review FPGA reconfiguration, looking at architectures built for the purpose, and the properties of modern commercial architectures. We then investigate design flows, and identify the key challenges in making reconfigurable FPGA systems easier to design. Finally, we look at applications where reconfiguration has found use, as well as proposing new areas where this capability places FPGAs in a unique position for adoption

Radiation safety based on the sky shine effect in reactor

In the reactor operation, neutrons and gamma rays are the most dominant radiation. As protection, lead and concrete shields are built around the reactor. However, the radiation can penetrate the water shielding inside the reactor pool. This incident leads to the occurrence of sky shine where a physical phenomenon of nuclear radiation sources was transmitted panoramic that extends to the environment. The effect of this phenomenon is caused by the fallout radiation into the surrounding area which causes the radiation dose to increase. High doses of exposure cause a person to have stochastic effects or deterministic effects. Therefore, this study was conducted to measure the radiation dose from sky shine effect that scattered around the reactor at different distances and different height above the reactor platform. In this paper, the analysis of the radiation dose of sky shine effect was measured using the experimental metho

Adaptation of High Performance and High Capacity Reconfigurable Systems to OpenCL Programming Environments

[EN] In this work, we adapt a reconfigurable computer system based on FPGA technologies to OpenCL programming environments. The reconfigurable system is part of a compute prototype of the MANGO European project that includes 96 FPGAs. To optimize the use and to obtain its maximum performance, it is essential to adapt it to heterogeneous systems programming environments such as OpenCL, which simplifies its programming. In this work, all the necessary activities for correct implementation of the software and hardware layer required for its use in OpenCL will be carried out, as well as an evaluation of the performance obtained and the flexibility offered by the solution provided. This work has been performed during an internship of 5 months. The internship is linked to an agreement between UPV and UniNa (Università degli Studi di Napoli Federico II).[ES] En este trabajo se va a realizar la adaptación de un sistema reconfigurable de cómputo basado en tecnologías de FPGAs hacia entornos de programación en OpenCL. El sistema reconfigurable forma parte de un prototipo de cálculo del proyecto Europeo MANGO que incluye 96 FPGAs. Con el fin de optimizar el uso y de obtener sus máximas prestaciones, se hace imprescindible una adaptación a entornos de programación de sistemas heterogéneos como OpenCL, lo cual simplifica su programación y uso. En este trabajo se realizarán todas las actividades necesarias para una correcta implementación de la capa software y hardware necesaria para su uso en OpenCL así como una evaluación de las prestaciones obtenidas y de la flexibilidad ofrecida por la solución aportada. Este trabajo se ha llevado a término durante una estancia de cinco meses en la Universitat Politécnica de Valéncia. Esta estancia está vinculada a un acuerdo entre la Universitat Politécnica de Valéncia y la Università degli Studi di Napoli Federico IIRusso, D. (2020). Adaptation of High Performance and High Capacity Reconfigurable Systems to OpenCL Programming Environments. http://hdl.handle.net/10251/150393TFG

Interconnect Planning for Physical Design of 3D Integrated Circuits

Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation.:1 Introduction 1.1 The 3D Integration Approach for Electronic Circuits 1.2 Technologies for 3D Integrated Circuits 1.3 Design Approaches for 3D Integrated Circuits 2 State of the Art in Design Automation for 3D Integrated Circuits 2.1 Thermal Management 2.2 Partitioning and Floorplanning 2.3 Placement and Routing 2.4 Power and Clock Delivery 2.5 Design Challenges 3 Research Objectives 4 Planning Through-Silicon Via Islands for Block-Level Design Reuse 4.1 Problems for Design Reuse in 3D Integrated Circuits 4.2 Connecting Blocks Using Through-Silicon Via Islands 4.2.1 Problem Formulation and Methodology Overview 4.2.2 Net Clustering 4.2.3 Insertion of Through-Silicon Via Islands 4.2.4 Deadspace Insertion and Redistribution 4.3 Experimental Investigation 4.3.1 Wirelength Estimation 4.3.2 Configuration 4.3.3 Results and Discussion 4.4 Summary and Conclusions 5 Planning Through-Silicon Vias for Design Optimization 5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias 5.2 Multiobjective Design Optimization of 3D Integrated Circuits 5.2.1 Methodology Overview and Configuration 5.2.2 Techniques for Deadspace Optimization 5.2.3 Design-Quality Analysis 5.2.4 Planning Different Types of Through-Silicon Vias 5.3 Experimental Investigation 5.3.1 Configuration 5.3.2 Results and Discussion 5.4 Summary and Conclusions 6 3D Floorplanning for Structural Planning of Massive Interconnects 6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits 6.2 Corner Block List Extended for Block Alignment 6.2.1 Alignment Encoding 6.2.2 Layout Generation: Block Placement and Alignment 6.3 3D Floorplanning Methodology 6.3.1 Optimization Criteria and Phases and Related Cost Models 6.3.2 Fast Thermal Analysis 6.3.3 Layout Operations 6.3.4 Adaptive Optimization Schedule 6.4 Experimental Investigation 6.4.1 Configuration 6.4.2 Results and Discussion 6.5 Summary and Conclusions 7 Research Summary, Conclusions, and Outlook Dissertation Theses Notation Glossary BibliographyDreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich.:1 Introduction 1.1 The 3D Integration Approach for Electronic Circuits 1.2 Technologies for 3D Integrated Circuits 1.3 Design Approaches for 3D Integrated Circuits 2 State of the Art in Design Automation for 3D Integrated Circuits 2.1 Thermal Management 2.2 Partitioning and Floorplanning 2.3 Placement and Routing 2.4 Power and Clock Delivery 2.5 Design Challenges 3 Research Objectives 4 Planning Through-Silicon Via Islands for Block-Level Design Reuse 4.1 Problems for Design Reuse in 3D Integrated Circuits 4.2 Connecting Blocks Using Through-Silicon Via Islands 4.2.1 Problem Formulation and Methodology Overview 4.2.2 Net Clustering 4.2.3 Insertion of Through-Silicon Via Islands 4.2.4 Deadspace Insertion and Redistribution 4.3 Experimental Investigation 4.3.1 Wirelength Estimation 4.3.2 Configuration 4.3.3 Results and Discussion 4.4 Summary and Conclusions 5 Planning Through-Silicon Vias for Design Optimization 5.1 Deadspace Requirements for Optimized Planning of Through-Silicon Vias 5.2 Multiobjective Design Optimization of 3D Integrated Circuits 5.2.1 Methodology Overview and Configuration 5.2.2 Techniques for Deadspace Optimization 5.2.3 Design-Quality Analysis 5.2.4 Planning Different Types of Through-Silicon Vias 5.3 Experimental Investigation 5.3.1 Configuration 5.3.2 Results and Discussion 5.4 Summary and Conclusions 6 3D Floorplanning for Structural Planning of Massive Interconnects 6.1 Block Alignment for Interconnects Planning in 3D Integrated Circuits 6.2 Corner Block List Extended for Block Alignment 6.2.1 Alignment Encoding 6.2.2 Layout Generation: Block Placement and Alignment 6.3 3D Floorplanning Methodology 6.3.1 Optimization Criteria and Phases and Related Cost Models 6.3.2 Fast Thermal Analysis 6.3.3 Layout Operations 6.3.4 Adaptive Optimization Schedule 6.4 Experimental Investigation 6.4.1 Configuration 6.4.2 Results and Discussion 6.5 Summary and Conclusions 7 Research Summary, Conclusions, and Outlook Dissertation Theses Notation Glossary Bibliograph

Physical design methodologies for monolithic 3D ICs

The objective of this research is to develop physical design methodologies for monolithic 3D ICs and use them to evaluate the improvements in the power-performance envelope offered over 2D ICs. In addition, design-for-test (DfT) techniques essential for the adoption of shorter term through-silicon-via (TSV) based 3D ICs are explored. Testing of TSV-based 3D ICs is one of the last challenges facing their commercialization. First, a pre-bond testable 3D scan chain construction technique is developed. Next, a transition-delay-fault test architecture is presented, along with a study on how to mitigate IR-drop. Finally, to facilitate partitioning, a quick and accurate framework for test-TSV estimation is developed. Block-level monolithic 3D ICs will be the first to emerge, as significant IP can be reused. However, no physical design flows exist, and hence a monolithic 3D floorplanning framework is developed. Next, inter-tier performance differences that arise due to the not yet mature fabrication process are investigated and modeled. Finally, an inter-tier performance-difference aware floorplanner is presented, and it is demonstrated that high quality 3D floorplans are achievable even under these inter-tier differences. Monolithic 3D offers sufficient integration density to place individual gates in three dimensions and connect them together. However, no tools or techniques exist that can take advantage of the high integration density offered. Therefore, a gate-level framework that leverages existing 2D ICs tools is presented. This framework also provides congestion modeling and produces results that minimize routing congestion. Next, this framework is extended to commercial 2D IC tools, so that steps such as timing optimization and clock tree synthesis can be applied. Finally, a voltage-drop-aware partitioning technique is presented that can alleviate IR-drop issues, without any impact on the performance or maximum operating temperature of the chip.Ph.D