1,657 research outputs found

    Compact and accurate models of large single-wall carbon-nanotube interconnects

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    Single-wall carbon nanotubes (SWCNTs) have been proposed for very large scale integration interconnect applications and their modeling is carried out using the multiconductor transmission line (MTL) formulation. Their time-domain analysis has some simulation issues related to the high number of SWCNTs within each bundle, which results in a highly complex model and loss of accuracy in the case of long interconnects. In recent years, several techniques have been proposed to reduce the complexity of the model whose accuracy decreases as the interconnection length increases. This paper presents a rigorous new technique to generate accurate reduced-order models of large SWCNT interconnects. The frequency response of the MTL is computed by using the spectral form of the dyadic Green's function of the 1-D propagation problem and the model complexity is reduced using rational-model identification techniques. The proposed approach is validated by numerical results involving hundreds of SWCNTs, which confirm its capability of reducing the complexity of the model, while preserving accuracy over a wide frequency range

    Modeling of Thermally Aware Carbon Nanotube and Graphene Based Post CMOS VLSI Interconnect

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    This work studies various emerging reduced dimensional materials for very large-scale integration (VLSI) interconnects. The prime motivation of this work is to find an alternative to the existing Cu-based interconnect for post-CMOS technology nodes with an emphasis on thermal stability. Starting from the material modeling, this work includes material characterization, exploration of electronic properties, vibrational properties and to analyze performance as a VLSI interconnect. Using state of the art density functional theories (DFT) one-dimensional and two-dimensional materials were designed for exploring their electronic structures, transport properties and their circuit behaviors. Primarily carbon nanotube (CNT), graphene and graphene/copper based interconnects were studied in this work. Being reduced dimensional materials the charge carriers in CNT(1-D) and in graphene (2-D) are quantum mechanically confined as a result of this free electron approximation fails to explain their electronic properties. For same reason Drude theory of metals fails to explain electronic transport phenomena. In this work Landauer transport theories using non-equilibrium Green function (NEGF) formalism was used for carrier transport calculation. For phonon transport studies, phenomenological Fourier’s heat diffusion equation was used for longer interconnects. Semi-classical BTE and Landauer transport for phonons were used in cases of ballistic phonon transport regime. After obtaining self-consistent electronic and thermal transport coefficients, an equivalent circuit model is proposed to analyze interconnects’ electrical performances. For material studies, CNTs of different variants were analyzed and compared with existing copper based interconnects and were found to be auspicious contenders with integrational challenges. Although, Cu based interconnect is still outperforming other emerging materials in terms of the energy-delay product (1.72 fJ-ps), considering the electromigration resistance graphene Cu hybrid interconnect proposed in this dissertation performs better. Ten times more electromigration resistance is achievable with the cost of only 30% increase in energy-delay product. This unique property of this proposed interconnect also outperforms other studied alternative materials such as multiwalled CNT, single walled CNT and their bundles

    Analysis of crosstalk and field coupling to lossy MTL's in a SPICE environment

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    This paper proposes a circuit model for lossy multiconductor transmission lines (MTLs) suitable for implementation in modern SPICE simulators, as well as in any simulator supporting differential operators. The model includes the effects of a uniform or nonuniform disturbing field illuminating the line and is especially devised for the transient simulation of electrically long wideband interconnects with frequency dependent per-unit-length parameters. The MTL is characterized by its transient matched scattering responses, which are computed including both dc and skin losses by means of a specific algorithm for the inversion of the Laplace transform. The line characteristics are then represented in terms of differential operators and ideal delays to improve the numerical efficiency and to simplify the coding of the model in existing simulators. The model can be successfully applied to many kinds of interconnects ranging from micrometric high-resistivity metallizations to low-loss PCBs and cables, and can be considered a practical extension of the widely appreciated lossless MTL SPICE model, which maintains the simplicity and efficienc

    SIM-DSP: A DSP-Enhanced CAD Platform for Signal Integrity Macromodeling and Simulation

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    Macromodeling-Simulation process for signal integrity verifications has become necessary for the high speed circuit system design. This paper aims to introduce a “VLSI Signal Integrity Macromodeling and Simulation via Digital Signal Processing Techniques” framework (known as SIM-DSP framework), which applies digital signal processing techniques to facilitate the SI verification process in the pre-layout design phase. Core identification modules and peripheral (pre-/post-)processing modules have been developed and assembled to form a verification flow. In particular, a single-step discrete cosine transform truncation (DCTT) module has been developed for modeling-simulation process. In DCTT, the response modeling problem is classified as a signal compression problem, wherein the system response can be represented by a truncated set of non-pole based DCT bases, and error can be analyzed through Parseval’s theorem. Practical examples are given to show the applicability of our proposed framework

    Carbon Nanotube Interconnect Modeling for Very Large Scale Integrated Circuits

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    In this research, we have studied and analyzed the physical and electrical properties of carbon nanotubes. Based on the reported models for current transport behavior in non-ballistic CNT-FETs, we have built a dynamic model for non-ballistic CNT-FETs. We have also extended the surface potential model of a non-ballistic CNT-FET to a ballistic CNT-FET and developed a current transport model for ballistic CNT-FETs. We have studied the current transport in metallic carbon nanotubes. By considering the electron-electron interactions, we have modified two-dimensional fluid model for electron transport to build a semi-classical one-dimensional fluid model to describe the electron transport in carbon nanotubes, which is regarded as one-dimensional system. Besides its accuracy compared with two-dimensional fluid model and Lüttinger liquid theory, one-dimensional fluid model is simple in mathematical modeling and easier to extend for electronic transport modeling of multi-walled carbon nanotubes and single-walled carbon nanotube bundles as interconnections. Based on our reported one-dimensional fluid model, we have calculated the parameters of the transmission line model for the interconnection wires made of single-walled carbon nanotube, multi-walled carbon nanotube and single-walled carbon nanotube bundle. The parameters calculated from these models show close agreements with experiments and other proposed models. We have also implemented these models to study carbon nanotube for on-chip wire inductors and it application in design of LC voltage-controlled oscillators. By using these CNT-FET models and CNT interconnects models, we have studied the behavior of CNT based integrated circuits, such as the inverter, ring oscillator, energy recovery logic; and faults in CNT based circuits

    Carbon nanotubes as interconnect for next generation network on chip

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    Multi-core processors provide better performance when compared with their single-core equivalent. Recently, Networks-on-Chip (NoC) have emerged as a communication methodology for multi core chips. Network-on-Chip uses packet based communication for establishing a communication path between multiple cores connected via interconnects. Clock frequency, energy consumption and chip size are largely determined by these interconnects. According to the International Technology Roadmap for Semiconductors (ITRS), in the next five years up to 80% of microprocessor power will be consumed by interconnects. In the sub 100nm scaling range, interconnect behavior limits the performance and correctness of VLSI systems. The performance of copper interconnects tend to get reduced in the sub 100nm range and hence we need to examine other interconnect options. Single Wall Carbon Nanotubes exhibit better performance in sub 100nm processing technology due to their very large current carrying capacity and large electron mean free paths. This work suggests using Single Wall Carbon Nanotubes (SWCNT) as interconnects for Networks-on-Chip as they consume less energy and gives more throughput and bandwidth when compared with traditional Copper wires
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