The Design of a single chip 8x8 ATM switch in 0.5 micrometers CMOS VLSI

This thesis illustrates the design of a single chip Asynchronous Transfer Mode (ATM) protocol switch using Very Large Scale Integration (VLSI). The ATM protocol is the data communications protocol used in the implementation of the Broadband Integrated Services Digital Network (B-ISDN), A number of switch architecture are first studied and a new architecture is developed based on optimizing performance and practicality of implementation in VLSI. A fully interconnected switch architecture is implemented by permanently connecting every input port to all the output ports. An output buffering scheme is used to handle cells that cannot be routed right away. This new architecture is caned the High Performance (HiPer) Switch Architecture. The performance of the architecture is simulated using a C++ model. Simulation results for a randomly distributed traffic pattern with a 90% probability of cells arriving in a time slot produces a Cell Loss Ratio of 1.Ox 10^-8 with output buffers that can hold 64 cells. The device is then modeled in VHDL to verify its functionality. Finally the layout of an 8x8 switch is produced using a 0.5 micrometer CMOS VLSI process and simulations of that circuit show that a peak throughput of 200 Mbps per output port can be achieve

Design of a scheduling mechanism for an ATM switch

Includes bibliographical references.In this dissenation, the candidate proposes the use of a ratio to multiply the weights used in the matching algorithm to control the delay that individual connections encounter. We demonstrate the improved characteristics of a switch using a ratio presenting results from simulations. The candidate also proposes a novel scheduling mechanism for an input queued ATM switch. In order to evaluate the performance of the scheduling mechanism in terms of throughput and fairness, the use of various metrics, initially proposed in the literature to evaluate output buffered switches are evaluated, adjusted and applied to input scheduling. In particular the Worst-case Fairness Index (WFl) which measures the maximum delay a connection will encounter is derived for use in input queued switches

NASA SERC 1990 Symposium on VLSI Design

This document contains papers presented at the first annual NASA Symposium on VLSI Design. NASA's involvement in this event demonstrates a need for research and development in high performance computing. High performance computing addresses problems faced by the scientific and industrial communities. High performance computing is needed in: (1) real-time manipulation of large data sets; (2) advanced systems control of spacecraft; (3) digital data transmission, error correction, and image compression; and (4) expert system control of spacecraft. Clearly, a valuable technology in meeting these needs is Very Large Scale Integration (VLSI). This conference addresses the following issues in VLSI design: (1) system architectures; (2) electronics; (3) algorithms; and (4) CAD tools

Analytical models for the multiplexing of worst case traffic sources and their application to ATM traffic control.

Postprint (published version

Algorithmic aspects of high speed switching

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Civil and Environmental Engineering, 2002.Includes bibliographical references (p. 145-148).A major drawback of the traditional output queuing technique is that it requires a switch speedup of N, where N is the size of the switch. This dependence on N makes the switch non-scalable at high speeds. Input queuing has been suggested instead. The introduction of input queuing creates the necessity for developing switching algorithms to decide which packets to keep waiting at the input, and which packets to forward across the switch. In this thesis, we address various algorithmic aspects of switching. We prove in this thesis, that many of the practical switching algorithms still require a speedup to achieve even a weak notion of throughput. We propose two switching algorithms that belong to a family to which we refer in this thesis as priority switching. These two algorithms overcome some of the disadvantages in existing priority switching algorithms, such as the excessive amount of state information that needs to be maintained. We also develop a practical algorithm that belongs to a family to which we refer in this thesis as iterative switching. This algorithm achieves high throughput in practice and offers the advantage of not requiring more than one iteration, unlike other existing iterative switching algorithms which require multiple iterations to achieve high throughput. Finally, we address the issue of using switches in parallel to accommodate for the need of speedup. We study two settings of parallel switches, one with standard packet switching, and one with flow scheduling, in which flows cannot be split across multiple switches.by Saadeddine Mneimneh.Ph.D