On-Line Dependability Enhancement of Multiprocessor SoCs by Resource Management

This paper describes a new approach towards dependable design of homogeneous multi-processor SoCs in an example satellite-navigation application. First, the NoC dependability is functionally verified via embedded software. Then the Xentium processor tiles are periodically verified via on-line self-testing techniques, by using a new IIP Dependability Manager. Based on the Dependability Manager results, faulty tiles are electronically excluded and replaced by fault-free spare tiles via on-line resource management. This integrated approach enables fast electronic fault detection/diagnosis and repair, and hence a high system availability. The dependability application runs in parallel with the actual application, resulting in a very dependable system. All parts have been verified by simulation

Heuristics for Routing and Spiral Run-time Task Mapping in NoC-based Heterogeneous MPSOCs

This paper describes a new Spiral Dynamic Task Mapping heuristic for mapping applications onto NoC-based Heterogeneous MPSoC. The heuristic proposed in this paper attempts to map the tasks of an applications that are most related to each other in spiral manner and to find the best possible path load that minimizes the communication overhead. In this context, we have realized a simulation environment for experimental evaluations to map applications with varying number of tasks onto an 8x8 NoC-based Heterogeneous MPSoCs platform, we demonstrate that the new mapping heuristics with the new modified dijkstra routing algorithm proposed are capable of reducing the total execution time and energy consumption of applications when compared to state-of the-art run-time mapping heuristics reported in the literature

Heuristics for Routing and Spiral Run-time Task Mapping in NoC-based Heterogeneous MPSOCs

Abstract This paper describes a new Spiral Dynamic Task Mapping heuristic for mapping applications onto NoC-based Heterogeneous MPSoC. The heuristic proposed in this paper attempts to map the tasks of an applications that are most related to each other in spiral manner and to find the best possible path load that minimizes the communication overhead. In this context, we have realized a simulation environment for experimental evaluations to map applications with varying number of tasks onto an 8x8 NoC-based Heterogeneous MPSoCs platform, we demonstrate that the new mapping heuristics with the new modified dijkstra routing algorithm proposed are capable of reducing the total execution time and energy consumption of applications when compared to state-of the-art run-time mapping heuristics reported in the literature

Statistical Learning in Chip (SLIC) (Invited Paper)

Abstract-Despite best efforts, integrated systems are "born" (manufactured) with a unique 'personality' that stems from our inability to precisely fabricate their underlying circuits, and create software a priori for controlling the resulting uncertainty. It is possible to use sophisticated test methods to identify the bestperforming systems but this would result in unacceptable yields and correspondingly high costs. The system personality is further shaped by its environment (e.g., temperature, noise and supply voltage) and usage (i.e., the frequency and type of applications executed), and since both can fluctuate over time, so can the system's personality. Systems also "grow old" and degrade due to various wear-out mechanisms (e.g., negative-bias temperature instability), and unexpectedly due to various early-life failure sources. These "nature and nurture" influences make it extremely difficult to design a system that will operate optimally for all possible personalities. To address this challenge, we propose to develop statistical learning in-chip (SLIC). SLIC is a holistic approach to integrated system design based on continuously learning key personality traits on-line, for selfevolving a system to a state that optimizes performance hierarchically across the circuit, platform, and application levels. SLIC will not only optimize integrated-system performance but also reduce costs through yield enhancement since systems that would have before been deemed to have weak personalities (unreliable, faulty, etc.) can now be recovered through the use of SLIC

An efficient task mapping algorithm with power-aware optimization for network on chip

More and more cores are integrated onto a single chip to improve the performance and reduce the power consumption of CPU without the increased frequency. The cores are connected by lines and organized as a network, which is called network on chip (NOC) as the promising paradigm of the processor design. However, it is still a challenge to enhance performance with lower power consumption. The core issue is how to map the tasks to the different cores to take full advantages of the on-chip network. In this paper, we proposed a novel mapping algorithm with power-aware optimization for NOC. The traffic of the tasks will be analyzed. The tasks of the same application with high communication with the others will be mapped to the on-chip network as neighborhoods. And then the tasks of different applications are mapped to the cores step by step. The mapping of the tasks and the cores is computed at run-time dynamically and implement online. The experimental results showed that this proposed algorithm can reduce the power consumption in communication and the performance enhanced

A Survey and Comparative Study of Hard and Soft Real-time Dynamic Resource Allocation Strategies for Multi/Many-core Systems

Multi-/many-core systems are envisioned to satisfy the ever-increasing performance requirements of complex applications in various domains such as embedded and high-performance computing. Such systems need to cater to increasingly dynamic workloads, requiring efficient dynamic resource allocation strategies to satisfy hard or soft real-time constraints. This article provides an extensive survey of hard and soft real-time dynamic resource allocation strategies proposed since the mid-1990s and highlights the emerging trends for multi-/many-core systems. The survey covers a taxonomy of the resource allocation strategies and considers their various optimization objectives, which have been used to provide comprehensive comparison. The strategies employ various principles, such as market and biological concepts, to perform the optimizations. The trend followed by the resource allocation strategies, open research challenges, and likely emerging research directions have also been provided

Power aware scheduler for heterogeneous environments

Dissertação de mestrado em Computer ScienceEfficient or green computing is becoming a key issue in current programming techniques, going beyond high performance computing, by simultaneously considering issues such as energy or power consumption. In heterogeneous environments, where different processors and accelerators co-processors may coexist, there is a real opportunity to reduce the overall energy consumption of the system by using scheduling decisions in run-time that can have a good and quick response to changes in the different components. Current tools to aid the development of efficient applications lack yet these run-time facilities. This motivated the development of a new framework with a power-aware scheduler for heterogeneous environments, PASH-Frame, whose prototype is the key object of this dissertation. This work extended previous performance-based scheduling work to include run-time power-aware features, adding tools to measure power consumption at each device and using different scheduling decisions to get the best outcome according to pre-defined targets by the end user. To evaluate the overall behaviour of PASH-Frame, several tests were performed: 1000 SAXPY tasks with vector sizes varying from 16 thousand elements to 256 thousand; 200 SGEMM tasks with matrices varying from 64 thousand elements to 16 million and finally a test that combines the two previous ones. Results show that the scheduling algorithm implemented in the framework can achieve good results in some cases, in spite of not being able to make some critical decisions when it comes to energy consumption reduction like forcing a component to idle to save energy.Computação eficiente (ou green computing) está a tornar-se um dos maiores desafios nas técnicas de programação actuais, considerando simultâneamente os problemas de computação de alta performance bem como a energia e o consumo total. Em ambientes heterogéneos, onde diferentes processadores e aceleradores como co-processadores podem coexistir, existe uma grande oportunidade para reduzir o consumo energético global do sistema ao utilizar decisões de escalonamento em tempo real que conseguem ter uma boa resposta rápida a mudanças nos diferentes componentes. As ferramentas actuais para ajudar na programação de aplicações eficientes ainda não têm estas ferramentas de leitura de energia em tempo real. Isto serviu de motivação para criar uma nova framework com um escalonador para sistemas heterogéneos consiente do gasto de energia, a PASH-Frame, em que o seu protótipo vai ser explicado nesta dissertação. Este trabalho é uma continuação de trabalho prévio em escalonamento baseado em alta performance ao incluir ferramentas de medição de energia em tempo real e ao fornecer decisões de escalonamento baseadas nesses valores para ter o melhor desempenho de acordo com as escolhas do seu utilizador. Para avaliar o comportamento da PASH-Frame, vários testes foram feitos: o primeiro teste foi de 1000 tarefas do algoritmo SAXPY com o tamanho dos vetores a variar entre 16 mil elementos e 256 mil; o segundo teste foi de 200 tarefas do algoritmo SGEMM com os tamanhos das matrizes a variar entre 64 mil elementos e 16 milhões de elementos e por fim o terceiro teste é uma combinação dos dois primeiros. Os resultados obtidos mostram que o algoritmo de escalonamento implementado na framework consegue obter bons resultados em alguns casos, apesar de não conseguir fazer algumas decisões críticas para o escalonamento com vista a reduzir o consumo global do sistema, como forçar um componente a ficar inativo para poupar energia

Dynamic task scheduling and binding for many-core systems through stream rewriting

This thesis proposes a novel model of computation, called stream rewriting, for the specification and implementation of highly concurrent applications. Basically, the active tasks of an application and their dependencies are encoded as a token stream, which is iteratively modified by a set of rewriting rules at runtime. In order to estimate the performance and scalability of stream rewriting, a large number of experiments have been evaluated on many-core systems and the task management has been implemented in software and hardware.In dieser Dissertation wurde Stream Rewriting als eine neue Methode entwickelt, um Anwendungen mit einer großen Anzahl von dynamischen Tasks zu beschreiben und effizient zur Laufzeit verwalten zu können. Dabei werden die aktiven Tasks in einem Datenstrom verpackt, der zur Laufzeit durch wiederholtes Suchen und Ersetzen umgeschrieben wird. Um die Performance und Skalierbarkeit zu bestimmen, wurde eine Vielzahl von Experimenten mit Many-Core-Systemen durchgeführt und die Verwaltung von Tasks über Stream Rewriting in Software und Hardware implementiert

Software-based and regionally-oriented traffic management in Networks-on-Chip

Since the introduction of chip-multiprocessor systems, the number of integrated cores has been steady growing and workload applications have been adapted to exploit the increasing parallelism. This changed the importance of efficient on-chip communication significantly and the infrastructure has to keep step with these new requirements. The work at hand makes significant contributions to the state-of-the-art of the latest generation of such solutions, called Networks-on-Chip, to improve the performance, reliability, and flexible management of these on-chip infrastructures