High-Performance Energy-Efficient and Reliable Design of Spin-Transfer Torque Magnetic Memory

In this dissertation new computing paradigms, architectures and design philosophy are proposed and evaluated for adopting the STT-MRAM technology as highly reliable, energy efficient and fast memory. For this purpose, a novel cross-layer framework from the cell-level all the way up to the system- and application-level has been developed. In these framework, the reliability issues are modeled accurately with appropriate fault models at different abstraction levels in order to analyze the overall failure rates of the entire memory and its Mean Time To Failure (MTTF) along with considering the temperature and process variation effects. Design-time, compile-time and run-time solutions have been provided to address the challenges associated with STT-MRAM. The effectiveness of the proposed solutions is demonstrated in extensive experiments that show significant improvements in comparison to state-of-the-art solutions, i.e. lower-power, higher-performance and more reliable STT-MRAM design

Multicomputer communication system

A local area network is provided for a plurality of autonomous computers which operate at different rates and under different protocols coupled by network bus adapters to a global bus. A host computer (HC) divides a message file to be transmitted into blocks, each with a header that includes a data type identifier and a trailer. The associated network bus adapter (NBA) then divides the data into packets, each with a header to which a transport header and trailer is added with frame type code which specifies one of three modes of addressing in the transmission of data, namely a physical address mode for computer to computer transmission using two bytes for source and destination addresses, a logical address mode and a data type mode. In the logical address mode, one of the two addressing bytes contains a logical channel number (LCN) established between the transmitting and one or more receiving computers. In the data type mode, one of the addressing bytes contains a code identifying the type of data

Error control coding for semiconductor memories

All modern computers have memories built from VLSI RAM chips. Individually, these devices are highly reliable and any single chip may perform for decades before failing. However, when many of the chips are combined in a single memory, the time that at least one of them fails could decrease to mere few hours. The presence of the failed chips causes errors when binary data are stored in and read out from the memory. As a consequence the reliability of the computer memories degrade. These errors are classified into hard errors and soft errors. These can also be termed as permanent and temporary errors respectively. In some situations errors may show up as random errors, in which both 1-to-O errors and 0-to-l errors occur randomly in a memory word. In other situations the most likely errors are unidirectional errors in which 1-to-O errors or 0-to-l errors may occur but not both of them in one particular memory word. To achieve a high speed and highly reliable computer, we need large capacity memory. Unfortunately, with high density of semiconductor cells in memory, the error rate increases dramatically. Especially, the VLSI RAMs suffer from soft errors caused by alpha-particle radiation. Thus the reliability of computer could become unacceptable without error reducing schemes. In practice several schemes to reduce the effects of the memory errors were commonly used. But most of them are valid only for hard errors. As an efficient and economical method, error control coding can be used to overcome both hard and soft errors. Therefore it is becoming a widely used scheme in computer industry today. In this thesis, we discuss error control coding for semiconductor memories. The thesis consists of six chapters. Chapter one is an introduction to error detecting and correcting coding for computer memories. Firstly, semiconductor memories and their problems are discussed. Then some schemes for error reduction in computer memories are given and the advantages of using error control coding over other schemes are presented. In chapter two, after a brief review of memory organizations, memory cells and their physical constructions and principle of storing data are described. Then we analyze mechanisms of various errors occurring in semiconductor memories so that, for different errors different coding schemes could be selected. Chapter three is devoted to the fundamental coding theory. In this chapter background on encoding and decoding algorithms are presented. In chapter four, random error control codes are discussed. Among them error detecting codes, single* error correcting/double error detecting codes and multiple error correcting codes are analyzed. By using examples, the decoding implementations for parity codes, Hamming codes, modified Hamming codes and majority logic codes are demonstrated. Also in this chapter it was shown that by combining error control coding and other schemes, the reliability of the memory can be improved by many orders. For unidirectional errors, we introduced unordered codes in chapter five. Two types of the unordered codes are discussed. They are systematic and nonsystematic unordered codes. Both of them are very powerful for unidirectional error detection. As an example of optimal nonsystematic unordered code, an efficient balanced code are analyzed. Then as an example of systematic unordered codes Berger codes are analyzed. Considering the fact that in practice random errors still may occur in unidirectional error memories, some recently developed t-random error correcting/all unidirectional error detecting codes are introduced. Illustrative examples are also included to facilitate the explanation. Chapter six is the conclusions of the thesis. The whole thesis is oriented to the applications of error control coding for semiconductor memories. Most of the codes discussed in the thesis are widely used in practice. Through the thesis we attempt to provide a review of coding in computer memories and emphasize the advantage of coding. It is obvious that with the requirement of higher speed and higher capacity semiconductor memories, error control coding will play even more important role in the future

Nutzung kryptographischer Funktionen zur Verbesserung der Systemzuverlässigkeit

Cryptographic techniques deal with securing information against unwanted usage, while coding techniques deals with keeping data error-free and retrieving them reliably. However, both techniques share many tools, bounds and limitations. In this thesis, several novel approaches towards improving system reliability by combining cryptographic and coding techniques in several constellations are presented. The first constellation is deploying pure cryptographic functions to improve reliability issues overshadowed in systems that previously had no reliability-supporting coding mechanisms. Such systems could have just authenticity, secrecy and/or integrity mechanisms for security services. The second constellation deploys a mixture of both cryptographic functions and error correction codes to improve the overall system reliability. The first contribution in this thesis, presents a new practical approach for detection and correction of execution errors for AES cipher. The source of such errors could be natural or as a result of fault injection attacks. The proposed approach is making use of the two linear mappings in the AES round structure for error control. The second contribution is investigating the possibility and ability of deploying pure cryptographic hash functions to detect and correct a class of errors. The error correction is achieved by deploying a part of the hash bits to correct a class of selected unidirectional error class with high probability. The error correction process would degrade the authentication level in a non-significant fashion. In the third and fourth contributions, we propose algorithms to improve system correctability beyond classical limits by combining coding and cryptographic functions. The new algorithms are based mainly on the fundamentals investigated in the second contribution as mechanisms to detect and correct errors. The new algorithms are investigated in terms of collision and attacking complexity, as error correction via hash matching is similar to a successful authentication attack. The resulting performance showed achievable good error correctability, authenticity, and integrity figures.Kryptografische Methoden zielen der Sicherung von Information gegen unerwünschte Nutzung, wobei Codierungstechnik behandelt die Korrektur der Fehler in den Daten und deren zuverlässigen Rückgewinnung. Beide Techniken bedienen sich ähnlich Instrumente und besitzen ähnliche grenzen und Grenzwerte. In diese Dissertation, werden mehrere neue Verfahren zur Verbesserung der Systemzuverlässigkeit durch verschiedene Konstellationen zur Kombination der beiden Fehlerkontrollcodierung und Kryptografische Verfahren. In der ersten Konstellation werden reine kryptologische Funktionen verwendet, die zur Verbesserung der Zuverlässigkeitsaspekte in den Systemen die keine Zuverlässigkeitsfördernde Codierungs-Maßnahme enthalten dienen. Solche Systeme besitzen z. B. nur Authentifikation, Geheimhaltung oder Integritäts-Mechanismen in den Sicherheitsdiensten. Die zweite Konstellation verwendet eine Kombination von Fehlerkorrigierende Codes und Krypto-Mechanismen für die Verbesserung der Zuverlässigkeit des Systems. Der erste Beitrag in diese Arbeit präsentiert ein neues praktisches Verfahren zur Erkennung und Korrektur von Verarbeitungsfehler in AES Chiffre. Die Ursachen solche Fehler konnten natürlich oder als Resultat eines beabsichtigten „Fault Injection“ Angriff sein. Das Verfahren nutzt die linearen Abbildungen im AES Runden-Funktion für Fehlerkontrolle. Der zweite Beitrag untersucht die Möglichkeit und Fähigkeit zur Einsatz von Hashfunktionen zur Erkennung und Korrektur vom Fehler. Die Fehlerkorrektur ist erreicht durch die Nutzung eines Anteil des Hash Bits um eine Klasse von ausgewähltem Unidirektionalen-Fehler mit höhe Wahrscheinlichkeit zu korrigieren. Dabei wird der Fehlerkorrekturprozess die Authentifikationsgrad des Hashfunktion nicht signifikant reduzieren. In den dritten und vierten Beitrag werden Algorithmen vorgeschlagen um die Zuverlässigkeit des System über die klassischen grenzen verbessert. Das wird durch Kombination von Kryptologischen und Codierung Funktionen erreicht. Die neuen Algorithmen sind auf die fundamentale Untersuchungen des zweiten Beitrag als Mechanismen für Fehlererkennung und Fehlerkorrektur basiert. Die neuen Algorithmen sind auf deren Kollision und Angriffskomplexität Verhalten untersucht worden, da Fehlerkorrektur durch Hashwert-Anpassung eines erfolgreichen Authentifikationsangriff ähnlich ist. Die resultierenden Verhalten zeigen gute Werte für erreichbare Fehlerkorrekturfähigkeit, Authentifikations-Grad und Integrität

Integer Codes Correcting Spotty Byte Asymmetric Errors

In short-range optical networks, channel errors occur due to energy losses. Upon transmission, they mostly manifest themselves as spotty byte asymmetric errors. In this letter, we present a class of codes that can correct these errors. The presented codes use integer and lookup table operations, which make them suitable for software implementation. In addition, if needed, the proposed codes can be interleaved without delay and without using any additional hardware

High Speed S-band Communications System for Nanosatellites

3Cat-3 is a nanosatellite based on the 6 unit cubesat standard. Its payload is an optical multispectral imager that imposes stringent downlink requirements for a nanosatellite. This TFG is based on the experience gained in 3Cat-1 and 3Cat-2 communications systems to develop a "high speed" (goal >= 5 Mbps) downlink for nanosatellites based on the TI CC3200.In order to accomplish the objectives of the next generation of nanosatellites high-speed downlinks have to be designed. This goal faces stringent design constraints as nanosatellites are limit in power, processing capabilities and dimensions. In the quest for higher bit rates the widely used VHF band has to be replaced for higher frequency bands and the link budged margin tightened, decreasing the SNR at reception. The proposed solution uses COTS 2.4 GHz WiFi adapters as transceivers. Range limitations imposed by the default 802.11 mode of operation are bypassed by using packet forging and injection at transmission jointly with monitor mode at reception. A loss-resilient unidirectional downlink is achieved by using application-layer encoding by means of LPDC-Staircase codes. This solution has been already implemented in 3CAT-2, a 6 unit cubesat GNSS-R mission to be launched in July 2016. In addition, bursts of errors are combated by using Reed-Solomon. The system has been tested under Doppler shift and scintillation effects, and a 188Km link between Barcelona and Mallorca has been performed, showing satisfactory results