Low power design of a 916 MHz Gilbert Cell Mixer and a Class-A Power Amplifier for Bioluminescent Bioreporter Integrated Circuit Transmitter

This thesis presents the low power design of a 916MHz Gilbert cell mixer and a Class-A power amplifier for the Bioluminescent Bioreporter Integrated Circuit (BBIC) transmitter. There has been increased use in the man-made sensors which can operate in environments unsuitable for humans and at locations remote from the observer. One such sensor is the bioluminescent bioreporter integrated circuit (BBIC). Bioluminescent bioreporters are the bacteria that are genetically engineered in order to achieve bioluminescence when in contact with the target substance. The BBIC has bioreporters placed on a single CMOS integrated circuit (IC) that detects the bioluminescence, performs the signal processing and finally transmits the senor data. The wireless transmission allows for remote sensing by eliminating the need of costly cabling to communicate with the sensor. The wireless data transmission is performed by the transmitter system. The digital data stream generated by the signal processing circuitry of the BBIC is ASK modulated for transmission. The direct conversion transmitter used in this design includes a PLL, Mixer and a Power amplifier. The PLL is used to generate a 916MHz frequency signal. This signal is mixed with the digital data signal generated from the signal processing circuitry of the BBIC. A double balanced Gilbert cell is used to perform the mixing operation. The mixer output is applied to a power amplifier which provides amplification of the RF output power. The Gilbert cell mixer and the power amplifier have been implemented in 90nm CMOS process available through MOSIS

System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system

On-Chip Analog Circuit Design Using Built-In Self-Test and an Integrated Multi-Dimensional Optimization Platform

Nowadays, the rapid development of system-on-chip (SoC) market introduces tremendous complexity into the integrated circuit (IC) design. Meanwhile, the IC fabrication process is scaling down to allow higher density of integration but makes the chips more sensitive to the process-voltage-temperature (PVT) variations. A successful IC product not only imposes great pressure on the IC designers, who have to handle wider variations and enforce more design margins, but also challenges the test procedure, leading to more check points and longer test time. To relax the designers’ burden and reduce the cost of testing, it is valuable to make the IC chips able to test and tune itself to some extent. In this dissertation, a fully integrated in-situ design validation and optimization (VO) hardware for analog circuits is proposed. It implements in-situ built-in self-test (BIST) techniques for analog circuits. Based on the data collected from BIST, the error between the measured and the desired performance of the target circuit is evaluated using a cost function. A digital multi-dimensional optimization engine is implemented to adaptively adjust the analog circuit parameters, seeking the minimum value of the cost function and achieving the desired performance. To verify this concept, study cases of a 2nd/4th active-RC band-pass filter (BPF) and a 2nd order Gm-C BPF, as well as all BIST and optimization blocks, are adopted on-chip. Apart from the VO system, several improved BIST techniques are also proposed in this dissertation. A single-tone sinusoidal waveform generator based on a finite-impulse-response (FIR) architecture, which utilizes an optimization algorithm to enhance its spur free dynamic range (SFDR), is proposed. It achieves an SFDR of 59 to 70 dBc from 150 to 850 MHz after the optimization procedure. A low-distortion current-steering two-tone sinusoidal signal synthesizer based on a mixing-FIR architecture is also proposed. The two-tone synthesizer extends the FIR architecture to two stages and implements an up-conversion mixer to generate the two tones, achieving better than -68 dBc IM3 below 480 MHz LO frequency without calibration. Moreover, an on-chip RF receiver linearity BIST methodology for continuous and discrete-time hybrid baseband chain is proposed. The proposed receiver chain implements a charge-domain FIR filter to notch the two excitation signals but expose the third order intermodulation (IM3) tones. It simplifies the linearity measurement procedure–using a power detector is enough to analyze the receiver’s linearity. Finally, a low cost fully digital built-in analog tester for linear-time-invariant (LTI) analog blocks is proposed. It adopts a time-to-digital converter (TDC) to measure the delays corresponded to a ramp excitation signal and is able to estimate the pole or zero locations of a low-pass LTI system

Reader Design for Chipless Millimeter-Wave Identification (MMID)TAG

RÉSUMÉ L’identification par radiofréquence (RFID) est une technologie d'identification qui a de nombreuses applications utiles telles que le suivi des marchandises et les contrôles d’accès. RFID est une technique de transmission et réception à courte distance « sans-contact » pour envoyer des données ID à un lecteur à partir d’un objet marqué. Un système RFID se compose d’une étiquette de support de données, un lecteur, un middleware et une application d'entreprise. Tout d'abord, le signal transmis est généré par le lecteur, après une certaine distance de transmission dans l'espace libre, l’étiquette reçoit le signal détecté et après le traitement de signal ou codage du signal sur l'étiquette, le signal codé est renvoyé au lecteur. La réception et le traitement du signal seront finalement faits au récepteur. Cependant, la technologie RFID est entravée en raison de son prix élevé. Les étiquettes RFID sans puce résolvent le problème de coût et ont le potentiel de pénétrer aux marchés en grand public pour l’étiquetage de l’article à faible coût. Pour les étiquettes sans puce il n'y a pas de traitement de signal. Le traitement du signal se fait uniquement au niveau du lecteur. Ainsi, un lecteur qui est utilisé pour communiquer avec l’étiquette est également important dans un système de communication. Le domaine de fréquence ou la signature spectrale en fonction des étiquettes sans puce est un type d’étiquette sans puce. D'autre part, l'émetteur et le récepteur se composent d'un lecteur. Basé sur le principe de fonctionnement des étiquettes sans puce dans le domaine de fréquence, un lecteur comprend un émetteur et un récepteur utilisés pour communiquer avec une étiquette de fréquence et est présenté dans cette thèse. Tout d'abord, le principe de fonctionnement détaillé du système MMID sans puce, dans le domaine fréquentiel est introduit. D'autre part, sur la base du principe de fonctionnement, les spécifications de la conception du lecteur sont proposées. Plusieurs topologies différentes de la conception du lecteur seront comparées et la meilleure topologie sera sélectionnée pour la conception du lecteur. En second lieu, sur la base des spécifications du système de lecture et de la topologie sélectionnée, les résultats de simulation de la structure sélectionnée de lecteur sont présentés. Après les simulations, la conception du chaque composant est montré. Dans cette conception de système des circuits, tous les circuits passifs sont conçus et simulés dans HFSS et mesurés sur VNA. Tous les circuits actifs sont des puces commerciale de différentes compagnies. Les résultats des simulations et mesures de chaque circuit passif sont affichés.----------ABSTRACT Radiofrequency identification (RFID) technology is an identification technology that has many useful applications such as tracking goods and access controls. RFID is a touchless, short distance transmission and reception technique for ID data that is sent from a labeled object to a reader. A data-carrying tag, a reader, middleware and an enterprise application would make up a RFID system. Firstly, the transmitted signal is generated by the reader, the tag receiver, after a certain distance of transmission in free space, a detected signal and after processing signal or encoding signal on the tag, the encoded signal is then sent back to the reader. Signal receiving and processing part will be finally processed in the receiver. However, the RFID technology is hindered because of its high price tag. Chipless RFID tags solve the cost issues and have the potential to penetrate into mass markets for low-cost item tagging. For chipless tags, there is no signal processing in tags, the signal processing is done only in the reader. So a reader, which is used to communicate with the tag, is also important in a communication system. Frequency domain or spectral signature-based chipless tags are some kinds of chipless tag. On the other hand, transmitter and receiver are the core parts of a reader, based on the working principle of frequency domain chipless tags, a reader that includes a transmitter and a receiver used to communicate with frequency tag is presented in this dissertation. First of all, the detailed working principle of a chipless MMID system in the frequency domain is introduced. Based on the working principle, the specifications of the reader design are proposed. Several different topologies of the reader design will be compared and the best topology will be selected for our reader design. Secondly, based on the specifications of the reader system and the selected topology, the simulation results of the selected structure of the reader are presented. After the simulations, the design of each component is shown. In this system design, all the passive circuits are designed and simulated in HFSS and tested on VNA. All the active circuits are commercial chips from different companies. Simulation and measurement results for each passive circuit are given. Finally, the whole circuits including designed passive circuits and active circuits are integrated into a system board to create a reader system. There are two system boards finally fabricated, one transmitter board and one completed reader board. The transmitter board is tested firstly. Upon achieving good results of the transmitter board, the whole transceiver board is tested finally

The Digital Signal Processing Platform for the Low Frequency Aperture Array: Preliminary Results on the Data Acquisition Unit

A signal processing hardware platform has been developed for the Low Frequency Aperture Array component of the Square Kilometre Array (SKA). The processing board, called an Analog Digital Unit (ADU), is able to acquire and digitize broadband (up to 500MHz bandwidth) radio-frequency streams from 16 dual polarized antennas, channel the data streams and then combine them flexibly as part of a larger beamforming system. It is envisaged that there will be more than 8000 of these signal processing platforms in the first phase of the SKA, so particular attention has been devoted to ensure the design is low-cost and low-power. This paper describes the main features of the data acquisition unit of such a platform and presents preliminary results characterizing its performance

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Design and Implementation of a Low‐Power Wireless Respiration Monitoring Sensor

Wireless devices for monitoring of respiration activities can play a major role in advancing modern home-based health care applications. Existing methods for respiration monitoring require special algorithms and high precision filters to eliminate noise and other motion artifacts. These necessitate additional power consuming circuitry for further signal conditioning. This dissertation is particularly focused on a novel approach of respiration monitoring based on a PVDF-based pyroelectric transducer. Low-power, low-noise, and fully integrated charge amplifiers are designed to serve as the front-end amplifier of the sensor to efficiently convert the charge generated by the transducer into a proportional voltage signal. To transmit the respiration data wirelessly, a lowpower transmitter design is crucial. This energy constraint motivates the exploration of the design of a duty-cycled transmitter, where the radio is designed to be turned off most of the time and turned on only for a short duration of time. Due to its inherent duty-cycled nature, impulse radio ultra-wideband (IR-UWB) transmitter is an ideal candidate for the implementation of a duty-cycled radio. To achieve better energy efficiency and longer battery lifetime a low-power low-complexity OOK (on-off keying) based impulse radio ultra-wideband (IR-UWB) transmitter is designed and implemented using standard CMOS process. Initial simulation and test results exhibit a promising advancement towards the development of an energy-efficient wireless sensor for monitoring of respiration activities

Radio-frequency integrated-circuit design for CMOS single-chip UWB systems

Low cost, a high-integrated capability, and low-power consumption are the basic requirements for ultra wide band (UWB) system design in order for the system to be adopted in various commercial electronic devices in the near future. Thus, the highly integrated transceiver is trended to be manufactured by companies using the latest silicon based complimentary metal-oxide-silicon (CMOS) processes. In this dissertation, several new structural designs are proposed, which provide solutions for some crucial RF blocks in CMOS for UWB for commercial applications. In this dissertation, there is a discussion of the development, as well as an illustration, of a fully-integrated ultra-broadband transmit/receive (T/R) switch which uses nMOS transistors with deep n-well in a standard 0.18-μm CMOS process. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET’s parasitic capacitances in order to synthesize artificial transmission lines which result in low insertion loss over an extremely wide bandwidth. Within DC-10 GHz, 10-18 GHz, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0 and 2.5 dB and isolation between 32-60 dB, 25-32 dB, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. Further, there is a discussion and demonstration of a tunable Carrier-based Time-gated UWB transmitter in this dissertation which uses a broadband multiplier, a novel fully integrated single pole single throw (SPST) switch designed by the CMOS process, where a tunable instantaneous bandwidth from 500 MHz to 4 GHz is exhibited by adjusting the width of the base band impulses in time domain. The SPST switch utilizes the synthetic transmission line concept and multiple reflections technique in order to realize a flat insertion loss less than 1.5 dB from 3.1 GHz to 10.6 GHz and an extremely high isolation of more than 45 dB within this frequency range. A fully integrated complementary LC voltage control oscillator (VCO), designed with a tunable buffer, operates from 4.6 GHz to 5.9 GHz. The measurement results demonstrate that the integrated VCO has a very low phase noise of –117 dBc/ Hz at 1 MHz offset. The fully integrated VCO achieves a very high figure of merit (FOM) of 183.5 using standard CMOS process while consuming 4 mA DC current