A transimpedance amplifier using a novel current mode feedback loop

We present a transimpedance amplifier stage based on a novel current mode feedback topology. This circuit employs NMOS and PMOS transistors exclusively and requires neither capacitor for stabilizing the transimpedance loop nor resistor for the transresistance feedback and transistor loading. This amplifier circuit is fully compatible with submicron digital CMOS processes. The active feedback network consists of two grounded-gate MOS devices which split the output current in both the feedback and output branches. The transresistance and the phase margin are adjustable through external DC signals. The measured rise time of the impulse response of the amplifier implemented in an industrial 0,7µm CMOS process is 18 ns for a transresistance of 180 k and 30 ns for a transresistance of 560 k. The measured Equivalent Noise Charge (ENC) is 800 rms e¯ for an input capacitance of 20 pF with the transresistance adjusted to 560 k

An 80 Mbit/s radiation-tolerant optical receiver for the CMS digital optical link

The CMS tracker slow control system will use approximately 1000 digital optical links for the transmission of timing, trigger and control signals. In this system, the 80 Mbit/s optical receiver at the detector end of each optical link has to be radiation hard since it will operate in the severe radiation environment of the CMS tracker (10 Mrad in 10 years). We have developed a prototype circuit in a 0.25 mu m commercial CMOS process using radiation tolerant layout practices to achieve the required radiation tolerance. This effective technique consists in the systematic use of enclosed (edgeless) NMOS transistors and guardrings, and relies in the natural total dose hardness of the thin gate oxide of deep submicron processes. The circuit features an automatic gain control loop allowing detection of wide dynamic range input signals (-20 to -3 d Bm) with minimum noise, compatible with the maximum expected radiation-induced drop in quantum efficiency of the PIN photodiode. A second feedback loop compensates a photodiode leakage current up to 100 mu A, and the circuit outputs an LVDS signal. Four receiver channels were integrated in a 2*2 mm/sup 2/ chip, out of which two were simultaneously bonded to two PIN photodiodes, and their BER performance was measured before and after an irradiation with 10 keV X-rays up to 20 Mrad (SiO/sub 2/). (11 refs)

Multipath feedforward compensated amplifier, related dipole (doublet) compression technique, and other topics

In order to truly realize entire mixed-signal systems on a chip and leverage the benefits of advanced process technologies, new low-voltage compatible amplifier topologies need to be developed.;In this context, a multipath-compensated multistage amplifier is introduced. These structures are compatible with low-voltage supplies because they use horizontal techniques (cascading) rather than vertical techniques (device stacking) to achieve large DC gains. When properly designed, these amplifiers are inherently first-order and do not suffer a reduction in the achievable gain-bandwidth product due to the process of compensation.;The technique relies upon pole-zero cancellation for proper operation. Absent techniques that ensure accurate cancellations, these architectures are not practical for high-speed applications. This is due to the fact that imperfect cancellations result in the appearance of slow-settling components in the transient response. To overcome this problem, structures that inherently ensure accurate cancellation or those that tune themselves to compensate for variations need to be developed.;A tuning strategy for a two-stage multipath-compensated amplifier was developed. It is based upon the observation that if the low-frequency pole leads the zero, the step-response is underdamped. Conversely, if the zero leads the pole, it is overdamped. By sensing the slope of the transient step response after a delay, the relationship between the location of the pole and the zero can be determined. Utilizing this information, a bias current is adjusted to modify the pole\u27s location relative to the zero. The process is repeated many times driving the mismatch down to an acceptable level. The concept was experimentally verified using a prototype fabricated in a 0.25mu CMOS process.;The insight gained in developing a tuning strategy for the two-stage amplifier has led to a methodology for tuning an amplifier with three or more stages. Preliminary simulations predict the technique is viable.;The thesis covers two additional topics as well. The first is a new CAD tool that enables designers to quickly understand the available design tradeoffs by interactive design space exploration. The second topic is a new transresistor circuit whose linearity is comparable to existing transresistors yet offers realizations that are simpler and more compact.*;*This dissertation is a compound document (contains both a paper copy and a CD as part of the dissertation). The CD requires the following system requirements: Adobe Acrobat; Microsoft Office; Windows MediaPlayer or RealPlayer; Internet browser; WinZip

Current mode monolithic active pixel sensor with correlated double sampling for charged particle detection

A monolithic active pixel sensor operating in current mode for charged particle detection is described. The sensing element in each pixel is an n-well/p-sub diode with a PMOS transistor integrated in an n-well. The drop of the n-well potential from the collection of charge modulates the transistor channel current. Each pixel features two current mode memory cells. The subtraction of distant-in-time samples frees the signal of fixed pattern noise (FPN) and of the correlated low-frequency temporal noise components, resulting in extraction of the particle footprint. The subtraction circuits are placed at each column end. A transimpedance amplifier, integrating in sequence two current samples and subtracting the results in an arithmetic operation, was adopted. The integrated version of the transimpedance amplifier, designed with a maximized conversion gain, is burdened by a risk of an early saturation, imperiling its operation, if the dispersions of the dc current component are too big. The degree of dispersions could not be estimated during the design. Some number of columns is available as a backup with the direct current readout. An external realization of the subtracting circuit, based on the same principle, is used to process direct output columns. The concept of the data acquisition setup developed, the tested performance of an array of cells, and the processing circuitry are described

Current Programmed Active Pixel Sensors for Large Area Diagnostic X-ray Imaging

Rapid progress over the last decade on large area thin film transistor (TFT) arrays led to the emergence of high-performance, low-power, low-cost active matrix flat panel imagers. Despite the shortcomings associated with the instability and low mobility of TFTs, the amorphous silicon TFT technology still remains the primary solution for the backplane of flat panel imagers. The use of a-Si:H TFTs as the building block of the large area integrated circuit becomes challenging particularly when the role of the TFT is extended from traditional switching applications to on-pixel signal amplifier for large area digital imaging. This is the idea behind active pixel sensor (APS) architectures in which under each pixel an amplifier circuit consisting of one or two switching TFTs integrated with one amplifying TFT is fabricated. To take advantage of the full potential of these amplifiers, it is crucial to develop APS architectures to compensate for the limitations of the TFTs. In this thesis several APS architectures are designed, simulated, fabricated, and tested addressing these challenges using the mask sets presented in Appendix A. The proposed APS architectures can compensate for inherent stabilities of the comprising TFTs. Therefore, the sensitivity of their output data to the transistor variations is significantly suppressed. This is achieved by using a well defined external current source instead of the traditional voltage source to reset the APS architectures during the reset cycle of their periodic operation. The performance of these circuits is analyzed in terms of their stability, settling time, noise, and temperature-dependence. For appropriate readout of the current mode APS architectures, high gain transresistance amplifiers with correlated double sampling capability is designed, simulated and fabricated in CMOS technology. Measurement and measurement based calculation results reveal that the proposed APS architectures can meet even the stringent requirements of low noise, real-time digital fluoroscopy

Wireless sensor platform for harsh environments

Reliable and efficient sensing becomes increasingly difficult in harsher environments. A sensing module for high-temperature conditions utilizes a digital, rather than analog, implementation on a wireless platform to achieve good quality data transmission. The module comprises a sensor, integrated circuit, and antenna. The integrated circuit includes an amplifier, A/D converter, decimation filter, and digital transmitter. To operate, an analog signal is received by the sensor, amplified by the amplifier, converted into a digital signal by the A/D converter, filtered by the decimation filter to address the quantization error, and output in digital format by the digital transmitter and antenna

Ultra low power circuits for a miniature apnoea detection device

Imperial Users onl

Silicon-germanium BiCMOS device and circuit design for extreme environment applications

Silicon-germanium (SiGe) BiCMOS technology platforms have proven invaluable for implementing a wide variety of digital, RF, and mixed-signal applications in extreme environments such as space, where maintaining high levels of performance in the presence of low temperatures and background radiation is paramount. This work will focus on the investigation of the total-dose radiation tolerance of a third generation complementary SiGe:C BiCMOS technology platform. Tolerance will be quantified under proton and X-ray radiation sources for both the npn and pnp HBT, as well as for an operational amplifier built with these devices. Furthermore, a technique known as junction isolation radiation hardening will be proposed and tested with the goal of improving the SEE sensitivity of the npn in this platform by reducing the charge collected by the subcollector in the event of a direct ion strike. To the author's knowledge, this work presents the first design and measurement results for this form of RHBD.M.S.Committee Chair: Cressler, John; Committee Member: Papapolymerou, John; Committee Member: Ralph, Stephe