Design, Characterization And Analysis Of Electrostatic Discharge (esd) Protection Solutions In Emerging And Modern Technologies

Electrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices’ operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and current density, as well as new failure mechanisms that are not well understood. The endeavor of this research is to develop novel, effective and robust ESD protection solutions for both emerging technologies and modern complementary metal–oxide–semiconductor (CMOS) technologies. The Si nanowire field-effect transistors are projected by the International Technology Roadmap for Semiconductors as promising next-generation CMOS devices due to their superior DC and RF performances, as well as ease of fabrication in existing Silicon processing. Aiming at proposing ESD protection solutions for nanowire based circuits, the dimension parameters, fabrication process, and layout dependency of such devices under Human Body Mode (HBM) ESD stresses are studied experimentally in company with failure analysis revealing the failure mechanism induced by ESD. The findings, including design methodologies, failure mechanism, and technology comparisons should provide practical knowhow of the development of ESD protection schemes for the nanowire based integrated circuits. Organic thin-film transistors (OTFTs) are the basic elements for the emerging flexible, printable, large-area, and low-cost organic electronic circuits. Although there are plentiful studies focusing on the DC stress induced reliability degradation, the operation mechanism of OTFTs iv subject to ESD is not yet available in the literature and are urgently needed before the organic technology can be pushed into consumer market. In this work, the ESD operation mechanism of OTFT depending on gate biasing condition and dimension parameters are investigated by extensive characterization and thorough evaluation. The device degradation evolution and failure mechanism under ESD are also investigated by specially designed experiments. In addition to the exploration of ESD protection solutions in emerging technologies, efforts have also been placed in the design and analysis of a major ESD protection device, diodetriggered-silicon-controlled-rectifier (DTSCR), in modern CMOS technology (90nm bulk). On the one hand, a new type DTSCR having bi-directional conduction capability, optimized design window, high HBM robustness and low parasitic capacitance are developed utilizing the combination of a bi-directional silicon-controlled-rectifier and bi-directional diode strings. On the other hand, the HBM and Charged Device Mode (CDM) ESD robustness of DTSCRs using four typical layout topologies are compared and analyzed in terms of trigger voltage, holding voltage, failure current density, turn-on time, and overshoot voltage. The advantages and drawbacks of each layout are summarized and those offering the best overall performance are suggested at the en

High-voltage ESD structures and ESD protection concepts in smart power technologies

Electro-static discharge (ESD) event can cause upset or permanent damage of integrated circuits (IC) and electrical systems. The risk of ESD fails needs to be mitigated or prevented. ESD robustness of IC products and electrical systems is specified, verified and qualified according to respective ESD standards. For high-voltage IC products based on smart power semiconductor technologies for industrial, power and automotive applications, design of effective and cost-efficient ESD protection is a big challenge, demanding wide and deep technical knowledge throughout high-frequency and high-power characterization techniques, semiconductor device physic, circuit design as well as modeling and simulation. The required measurement setups and tester components are developed and introduced. The characterization of ESD protection devices, IC and off-chip circuit elements is enabled and improved. The rise-time filters are important for the study of rise-time dependent ESD robustness. The human metal model (HMM) tester as an alternative to IEC ESD generators provides voltage waveform measurement with good quality in addition to current waveform measurement. It can be used for wafer-level or package-level device characterization. The measurement results of HMM tester and IEC ESD generator are compared. The on-chip ESD protection design relies on proper choice of different types of ESD protection devices and structures, depending on ESD specifications and IC applications. Typical on-chip ESD protection, whether snapback or non-snapback, single device or ESD circuit is introduced. The failure levels studies give a systematic benchmark of the ESD protection devices and structures, concerning device area, clamping voltage and other relevant parameters. The trade-off between those parameters and limitation of different ESD protection is discussed. Moreover, understanding of ESD failure modes is the key to implement effective ESD design. A unique ESD failure mode of smart power semiconductor device is discovered and investigated in detail. In the scope of finding ESD solutions, new active ESD clamps have been further developed in this work. The study of ESD protection is extended to the system-level involving on- and off-chip ESD protection elements. The characteristics of typical off-chip elements as well as the interaction between IC and off-chip protection elements plays essential role on the system robustness. A system-level ESD simulation incorporating IC and off-chip protection elements is desired for system efficient ESD design (SEED). A behavioral ESD model is developed which reproduces pulse-energy-dependent failure levels and self-heating effects. This modeling methodology can be used for assessment of system robustness even beyond ESD time-domain. The validation of the models is given by representative application examples. Several main challenges of high-voltage ESD design in smart power technologies have been addressed in this work, which can serve as guidance for ESD development and product support in future power semiconductor technologies

Modeling and simulation of full-component integrated circuits in transient ESD events

This thesis presents a methodology to model and simulate transient electrostatic discharge (ESD) responses of integrated circuits (IC). To obtain valid simulation results, the IC component must be represented by a circuit netlist composed of device models that are valid under the ESD conditions. Models of the nonlinear devices that make up the ESD protection network of the IC must have transient I-V responses calibrated against measurements that emulate ESD events. Interconnects, power distribution networks, and the silicon substrate on the chip die as well as on the IC package must be faithfully constructed to emulate the fact that ESD current flows in a distributed manner across the entire IC component. The resultant equivalent circuit model therefore contains a huge number of nodes and devices, and the simulation runtime may be prohibitively long. Techniques must be devised to make the numerical simulation process more efficient without sacrifice of accuracy. These techniques include reasonable abstraction of the distributed full-component circuit netlist, dynamic piecewise-linear device models, and customized efficient transient circuit simulator. With the simulation streamlining techniques set up properly, comprehensive and predictive transient ESD simulation can be carried out efficiently to investigate the weakest link in the target IC, and the design can be fine-tuned to achieve optimal performance in both functionality and ESD reliability

Hot-carrier reliability evaluation for CMOS devices and circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.Includes bibliographical references (p. 138-139).by Vei-Han Chan.Ph.D

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Modeling and control of undesirable dynamics in atomic force microscopes

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2002.Includes bibliographical references (leaves 156-165).The phenomenal resolution and versatility of the atomic force microscope (AFM), has made it a widely-used instrument in nanotechnology. In this thesis, a detailed model of AFM dynamics has been developed. It includes a new model for the piezoelectric scanner coupled longitudinal and lateral dynamics, creep, and hysteresis. Models for probe-sample interactions and cantilever dynamics were also included. The models were used to improve the dynamic response and hence image quality of contact-mode AFM. An extensive parametric study has been performed to experimentally analyze in-contact dynamics. Nonlinear variations in the frequency response were observed, in addition to changes in the pole-zero structure. The choice of scan parameters was found to have a major impact on image quality and feedback performance. Further, compensation for scanner creep was experimentally tested yielding a reduction in creep by a factor of 3 to 4 from the uncompensated system. Moreover, fundamental performance limitations in the AFM feedback system were identified. These limitations resulted in a severe bound on the maximum achievable feedback bandwidth, as well as a fundamental trade-off between step response overshoot and response time. A careful analysis has revealed that a PID controller has no real advantage over an integral controller.(cont.) Therefore, a procedure for automatically selecting key scan parameters and controller gain was developed and experimentally tested for I-control. This approach, in contrast to the commonly used trial and error method, can substantially improve image quality and fidelity. In addition, a robust adaptive output controller (RAOC), was designed to guarantee global boundedness and asymptotic regulation in the presence and absence of disturbances, respectively. Simulations have shown that a substantial reduction in contact force can be achieved with the RAOC, in comparison with a well-tuned I-controller, yet with no increase in the maximum scan speed. Furthermore, a new method was developed to allow calibrating the scanner's vertical displacement up to its full range, in addition to characterizing scanner hysteresis. This work has identified and addressed crucial problems and proposed practical solutions to factors limiting the dynamic performance of the AFM.by Osamah M. El Rifai.Ph.D

The 1st International Conference on Computational Engineering and Intelligent Systems

Computational engineering, artificial intelligence and smart systems constitute a hot multidisciplinary topic contrasting computer science, engineering and applied mathematics that created a variety of fascinating intelligent systems. Computational engineering encloses fundamental engineering and science blended with the advanced knowledge of mathematics, algorithms and computer languages. It is concerned with the modeling and simulation of complex systems and data processing methods. Computing and artificial intelligence lead to smart systems that are advanced machines designed to fulfill certain specifications. This proceedings book is a collection of papers presented at the first International Conference on Computational Engineering and Intelligent Systems (ICCEIS2021), held online in the period December 10-12, 2021. The collection offers a wide scope of engineering topics, including smart grids, intelligent control, artificial intelligence, optimization, microelectronics and telecommunication systems. The contributions included in this book are of high quality, present details concerning the topics in a succinct way, and can be used as excellent reference and support for readers regarding the field of computational engineering, artificial intelligence and smart system

Research reports: The 1980 NASA/ASEE Summer Faculty Fellowship Program

The Summer Faculty Fellowship Research Program objectives are: to further the professional knowledge of qualified engineering and science faculty members; to stimulate an exchange of ideas between participants and NASA; to enrich and refresh the research and teaching activities of participants and institutions; and to contribute to the research objectives at the NASA centers. The Faculty Fellows engaged in research projects commensurate with their interests and background and worked in collaboration with a NASA/MSFC colleague

Robust real-time control of an adaptive optics system

This research contributes to the understanding of the limitations when designing a robust control real-time system for Adaptive Optics (AO). One part of the research is a new method regarding the evaluation of a Shack-Hartmann wavefront sensor (SHWFS) to enhance the overall performance. The method is presented based on the application of a Field Programmable Gate Array (FPGA) using Connected Component Labeling (CCL) for blob detection. The FPGA has been utilized since the resulting delay is crucial for the general AO performance. In this regard, the FPGA may accelerate the evaluation largely by its parallelism. The developed algorithm does not rely on a fixed assignment of the camera sensor area to the lenslet array to maximize the dynamic range. In extension to the SHWFS evaluation, a new rapid control prototyping (RCP) system based on hard real-time RTAI-patched Linux kernel has been developed. This system includes the required hardware e.g.~the analog output cards and FPGA based frame-grabber. Based upon a Simulink model, accelerated C/C++ code is automatically generated which uses the available parallel features of the processor. A continuative contribution is the application of a robust control scheme using H-infinity methods for designing a controller while considering uncertainty of the identified model. For synthesizing the controller, a special optimization technique called non-smooth mu-synthesis is utilized which minimizes the H-infinity norm while coping with pre-specified controller schemes. Depending on the pre-specified controller scheme, the resulting controller can be computationally costly but the RCP approach is designed to cope with the problem. Based on simulations and according to experiments, the validity of the identified models of the AO setup is assured. At the same time, the enhanced performance of the new RCP setup is demonstrated.Die wissenschaftliche Arbeit trägt maßgeblich zum Verständnis der gängigen Limitierungen bei robusten echtzeit-fähigen Regelungssystemen für Adaptiv Optische (AO) Systeme bei. Ein wesentlicher Teil der Arbeit befasst sich mit einer neuartigen Methode der Auswertung eines Shack-Hartmann Wellenfrontsensors (SHWFS). Die Methode basiert auf der Anwendung eines Field Programmable Gate Arrays (FPGA) zur Auswertung des SHWFS. Die zu Grunde liegende Methode ist ein Resultat der Graphentheorie zur Erkennung zusammenhängender Bildbereiche. Der Einsatz eines FPGA ermöglicht hierbei, dass die resultierende Verzögerung durch die Auswertung des SHWFS auf ein Minimum reduziert wird. Hinzu kommt, dass die neuartige Auswertungsmethode den dynamischen Bereich des Wellenfrontsensors gegenüber dem üblichen Verfahren erweitert, da für die Methode keine feste Zuordnung der Spots zu dem Linsenarray notwendig ist. Zusätzlich zu dem neuartigen Verfahren für die Auswertung wurde ein Rapid Control Prototyping (RCP) System entworfen, welches auf einem echtzeitfähigen Linux Kernel basiert. Die Echtzeitfähigkeit wird durch die Verwendung des Real-Time Application Interface for Linux (RTAI) erreicht. Der Entwurf des RCP Systems umfasst die Entwicklung spezieller Hardware wie beispielsweise eine analoge Ausgangskarte und der PCIe FPGA Framegrabber. Aus einem Simulink Modell wird automatisch C/C++ Quellcode generiert. Dieser generierte Code nutzt die vorhandenen parallelen Erweiterungen des Prozessors zur Beschleunigung der vorkommenden Berechnungen. Basierend auf diesem System wurde ein robustes Regelungsverfahren angewendet, welches auf der H_infty Entwurfsmethodik basiert. Das Entwurfverfahren des Reglers (non-smooth mu Synthese) berücksichtigt die vorhandene Unsicherheit der identifizierten Modelle bereits während der Synthese. Das Verfahren ermöglicht die H_infty Norm des geschlossenen Regelkreises zu minimieren, wobei die Regler-Struktur vorgegeben werden kann. Basierend auf verschiedenen Simulationen und experimentellen Versuchen wurde die Gültigkeit der identifizierten Modelle des AO Systems nachgewiesen. Zudem wird gezeigt, dass das entworfene RCP System deutlich leistungsfähiger als vergleichbare Systeme ist und somit eine deutlich verbesserte Performance aufweist