Modeling and simulation of full-component integrated circuits in transient ESD events

Abstract

This thesis presents a methodology to model and simulate transient electrostatic discharge (ESD) responses of integrated circuits (IC). To obtain valid simulation results, the IC component must be represented by a circuit netlist composed of device models that are valid under the ESD conditions. Models of the nonlinear devices that make up the ESD protection network of the IC must have transient I-V responses calibrated against measurements that emulate ESD events. Interconnects, power distribution networks, and the silicon substrate on the chip die as well as on the IC package must be faithfully constructed to emulate the fact that ESD current flows in a distributed manner across the entire IC component. The resultant equivalent circuit model therefore contains a huge number of nodes and devices, and the simulation runtime may be prohibitively long. Techniques must be devised to make the numerical simulation process more efficient without sacrifice of accuracy. These techniques include reasonable abstraction of the distributed full-component circuit netlist, dynamic piecewise-linear device models, and customized efficient transient circuit simulator. With the simulation streamlining techniques set up properly, comprehensive and predictive transient ESD simulation can be carried out efficiently to investigate the weakest link in the target IC, and the design can be fine-tuned to achieve optimal performance in both functionality and ESD reliability