Controlled data storage for non-volatile memory cells embedded in nano magnetic logic

Among the beyond-CMOS technologies, perpendicular Nano Magnetic Logic (pNML) is a promising candidate due to its low power consumption, its non-volatility and its monolithic 3D integrability, which makes it possible to integrate memory and logic into the same device by exploiting the interaction of bi-stable nanomagnets with perpendicular magnetic anisotropy. Logic computation and signal synchronization are achieved by focus ion beam irradiation and by pinning domain walls in magnetic notches. However, in realistic circuits, the information storage and their read-out are crucial issues, often ignored in the exploration of beyond-CMOS devices. In this paper we address these issues by experimentally demonstrating a pNML memory element, whose read and write operations can be controlled by two independent pulsed currents. Our results prove the correct behavior of the proposed structure that enables high density memory embedded in the logic plane of 3D-integrated pNML circuits

New Logic-In-Memory Paradigms: An Architectural and Technological Perspective

Processing systems are in continuous evolution thanks to the constant technological advancement and architectural progress. Over the years, computing systems have become more and more powerful, providing support for applications, such as Machine Learning, that require high computational power. However, the growing complexity of modern computing units and applications has had a strong impact on power consumption. In addition, the memory plays a key role on the overall power consumption of the system, especially when considering data-intensive applications. These applications, in fact, require a lot of data movement between the memory and the computing unit. The consequence is twofold: Memory accesses are expensive in terms of energy and a lot of time is wasted in accessing the memory, rather than processing, because of the performance gap that exists between memories and processing units. This gap is known as the memory wall or the von Neumann bottleneck and is due to the different rate of progress between complementary metal-oxide semiconductor (CMOS) technology and memories. However, CMOS scaling is also reaching a limit where it would not be possible to make further progress. This work addresses all these problems from an architectural and technological point of view by: (1) Proposing a novel Configurable Logic-in-Memory Architecture that exploits the in-memory computing paradigm to reduce the memory wall problem while also providing high performance thanks to its flexibility and parallelism; (2) exploring a non-CMOS technology as possible candidate technology for the Logic-in-Memory paradigm

FUNCODE: Effective Device-to-System Analysis of Field Coupled Nanocomputing Circuit Designs

Many beyond-CMOS technologies, based on different switching mechanisms, are arising. Field-coupled technologies are the most promising as they can guarantee an extremely low-power consumption and combine logic and memory into the same device. However, circuit-level explorations, like layout verification and analysis of the circuit performance, considering the constraints of the target technology, cannot be done using existing tools. Here, we propose a methodology to take on this challenge. We present FUNCODE (FUNction & COnnection DEtection), an algorithm that can detect element connections, functions and errors of custom-layouts and generate its corresponding VHDL netlist. It is proposed for in-plane and perpendicular Nano Magnetic Logic as a case study. FUNCODE netlists, which take into account the physical behavior of the technology, were verified using circuits with increasing complexity, from 6 up to 1400 gates with a number of layout elements varying from 200 to 2.3e6

Two-Dimensional Spintronic Circuit Architectures on Large Scale Graphene

Solid-state electronics based on utilizing the electron spin degree of freedom for storing and processing information can pave the way for next-generation spin-based computing. However, the realization of spin communication between multiple devices in complex spin circuit geometries, essential for practical applications, is still lacking. Here, we demonstrate the spin current propagation in two-dimensional (2D) circuit architectures consisting of multiple devices and configurations using a large area CVD graphene on SiO2/Si substrate at room temperature. Taking advantage of the significant spin transport distance reaching 34 {\mu}m in commercially available wafer-scale graphene grown on Cu foil, we demonstrate that the spin current can be effectively communicated between the magnetic memory elements in graphene channels within 2D circuits of Y-junction and Hexa-arm architectures. We further show that by designing graphene channels and ferromagnetic elements at different geometrical angles, the symmetric and antisymmetric components of the Hanle spin precession signal can be remarkably controlled. These findings lay the foundation for the design of complex 2D spintronic circuits, which can be integrated into efficient electronics based on the transport of pure spin currents

Multilayer Nanomagnet Threshold Logic

Nanomagnet logic (NML) uses dipolar magnetic coupling between nanomagnets to efficiently perform nonvolatile logical operations. As the basis logic element, the three-input minority gate is the simplest threshold logic function. Recent work has explored the potential for increased logical expressivity with a nanomagnet threshold logic family that reduces area, delay, and energy costs. However, as such previous work was limited to a single layer of nanomagnets, only negative input weights could be provided, thus limiting circuit expressivity and efficiency. This article therefore, proposes multilayer nanomagnet threshold logic systems that provide both positive and negative weights by leveraging multilayer structures that produce both ferromagnetic and antiferromagnetic dipolar coupling. The availability of both positive and negative weights drastically increases logical expressivity, and the feasibility of the proposed multilayer nanomagnet threshold logic system is demonstrated through micromagnetic simulations. A single seven-input gate is shown to perform more than 86 distinct logic functions, reducing the number of gates and clock cycles required for complex logic circuits by as much as 67%

Nanomagnetic Self-Organizing Logic Gates

The end of Moore's law for CMOS technology has prompted the search for low-power computing alternatives, resulting in several promising proposals based on magnetic logic[1-8]. One approach aims at tailoring arrays of nanomagnetic islands in which the magnetostatic interactions constrain the equilibrium orientation of the magnetization to embed logical functionalities[9-12]. Despite the realization of several proofs of concepts of such nanomagnetic logic[13-15], it is still unclear what the advantages are compared to the widespread CMOS designs, due to their need for clocking[16, 17] and/or thermal annealing [18,19] for which fast convergence to the ground state is not guaranteed. In fact, it seems increasingly evident that "beyond CMOS" technology will require a fundamental rethinking of our computing paradigm[20]. In this respect, a type of terminal-agnostic logic was suggested[21], where a given gate is able to "self-organize" into its correct logical states, regardless of whether the signal is applied to the traditional input terminals, or the output terminals. Here, we introduce nanomagnetic self-organizing balanced logic gates, that employ stray-field coupled nanomagnetic islands to perform terminal-agnostic logic. We illustrate their capabilities by implementing reversible Boolean circuitry to solve a two-bit factorization problem via numerical modelling. In view of their design and mode of operation, we expect these systems to improve significantly over those suggested in Ref.[21], thus offering an alternative path to explore memcomputing, whose usefulness has already been demonstrated by solving a variety of hard combinatorial optimization problems[22]

Ta/CoFeB/MgO analysis for low power nanomagnetic devices

The requirement of high memory bandwidth for next-generation computing systems moved the attention to the development of devices that can combine storage and logic capabilities. Domain wall-based spintronic devices intrinsically combine both these requirements making them suitable both for non-volatile storage and computation. CoPt and CoNi were the technology drivers of perpendicular Nano Magnetic Logic devices (pNML), but for power constraints and depinning fields, novel CoFeBMgO layers appear more promis- ing. In this paper, we investigate the Ta2CoFeB1MgO2Ta3 stack at the simulation and experimental level, to show its potential for the next generation of magnetic logic devices. The micromagnetic simulations are used to support the experiments. We focus, first, at the experimental level measuring the switching field distribution of patterned magnetic islands, Ms via VSM and the domain wall speed on magnetic nanowires. Then, at the simulation level, we focus on the magnetostatic analysis of magnetic islands quantifying the stray field that can be achieved with different layout topologies. Our results show that the achieved coupling is strong enough to realize logic computation with magnetic islands, moving a step forward in the direction of low power perpendicularly magnetized logic devices