Wearable devices for aging polulation.

Este trabajo de fin de grado es parte de un proyecto del ministerio italiano de salud en el cual se intenta dar a conocer y analizar los diferentes dispostivos de ayuda para personas mayores o personas que puedan padecer alguna enfermedad. Para ello, analizaremos y estudiaremos los datos de diferentes modelos y dispostivos de diferentes sistemas de información y bases de datos intentado proporcionar una visión global sobre estos nuevos instrumentos tecnológicos que nos ayudan en la actualidad. Primeramente, se examinaran los datos recogidos y se realizarán estadísticas para ver su rendimiento en diferentes ámbitos como el análisis de la frecuencia cardiaca, medidor de calorías, detección de caídas... Finalmente, se estudiará el modo de transmisión de datos de cada modelo de dispositivo para dar a entender donde se almacén los datos y que mecanismo de transmisión se utilizan para recolectarlos.<br /

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Implementing embedded neural network processing at the edge requires efficient hardware acceleration that couples high computational performance with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly updated and improved. To evaluate and compare hardware design choices, designers can refer to a myriad of accelerator implementations in the literature. Surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effect of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. This work provides a survey of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. It presents the list of optimizations and their quantitative effects as a construction kit, allowing to assess the design choices for each building block separately. Reported optimizations range from up to 10'000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators

Femtocell Networks: A Survey

The surest way to increase the system capacity of a wireless link is by getting the transmitter and receiver closer to each other, which creates the dual benefits of higher quality links and more spatial reuse. In a network with nomadic users, this inevitably involves deploying more infrastructure, typically in the form of microcells, hotspots, distributed antennas, or relays. A less expensive alternative is the recent concept of femtocells, also called home base-stations, which are data access points installed by home users get better indoor voice and data coverage. In this article, we overview the technical and business arguments for femtocells, and describe the state-of-the-art on each front. We also describe the technical challenges facing femtocell networks, and give some preliminary ideas for how to overcome them.Comment: IEEE Communications Magazine, vol. 46, no.9, pp. 59-67, Sept. 200

Very-Large-Scale-Integration Circuit Techniques in Internet-of-Things Applications

Heading towards the era of Internet-of-things (IoT) means both opportunity and challenge for the circuit-design community. In a system where billions of devices are equipped with the ability to sense, compute, communicate with each other and perform tasks in a coordinated manner, security and power management are among the most critical challenges. Physically unclonable function (PUF) emerges as an important security primitive in hardware-security applications; it provides an object-specific physical identifier hidden within the intrinsic device variations, which is hard to expose and reproduce by adversaries. Yet, designing a compact PUF robust to noise, temperature and voltage remains a challenge. This thesis presents a novel PUF design approach based on a pair of ultra-compact analog circuits whose output is proportional to absolute temperature. The proposed approach is demonstrated through two works: (1) an ultra-compact and robust PUF based on voltage-compensated proportional-to-absolute-temperature voltage generators that occupies 8.3× less area than the previous work with the similar robustness and twice the robustness of the previously most compact PUF design and (2) a technique to transform a 6T-SRAM array into a robust analog PUF with minimal overhead. In this work, similar circuit topology is used to transform a preexisting on-chip SRAM into a PUF, which further reduces the area in (1) with no robustness penalty. In this thesis, we also explore techniques for power management circuit design. Energy harvesting is an essential functionality in an IoT sensor node, where battery replacement is cost-prohibitive or impractical. Yet, existing energy-harvesting power management units (EH PMU) suffer from efficiency loss in the two-step voltage conversion: harvester-to-battery and battery-to-load. We propose an EH PMU architecture with hybrid energy storage, where a capacitor is introduced in addition to the battery to serve as an intermediate energy buffer to minimize the battery involvement in the system energy flow. Test-case measurements show as much as a 2.2× improvement in the end-to-end energy efficiency. In contrast, with the drastically reduced power consumption of IoT nodes that operates in the sub-threshold regime, adaptive dynamic voltage scaling (DVS) for supply-voltage margin removal, fully on-chip integration and high power conversion efficiency (PCE) are required in PMU designs. We present a PMU–load co-design based on a fully integrated switched-capacitor DC-DC converter (SC-DC) and hybrid error/replica-based regulation for a fully digital PMU control. The PMU is integrated with a neural spike processor (NSP) that achieves a record-low power consumption of 0.61 µW for 96 channels. A tunable replica circuit is added to assist the error regulation and prevent loss of regulation. With automatic energy-robustness co-optimization, the PMU can set the SC-DC’s optimal conversion ratio and switching frequency. The PMU achieves a PCE of 77.7% (72.2%) at VIN = 0.6 V (1 V) and at the NSP’s margin-free operating point

Satisfaction-Aware Data Offloading in Surveillance Systems

In this thesis, exploiting Fully Autonomous Aerial Systems\u27 (FAAS) and Mobile Edge Computing (MEC) servers\u27 computing capabilities to introduce a novel data offloading framework to support the energy and time-efficient video processing in surveillance systems based on satisfaction games. A surveillance system is introduced consisting of Areas of Interest (AoIs), where a MEC server is associated with each AoI, and a FAAS is flying above the AoIs to support the IP cameras\u27 computing demands. Each IP camera adopts a utility function capturing its Quality of Service (QoS) considering the experienced time and energy overhead to offload and process remotely or locally the data. A non-cooperative game among the cameras is formulated to determine the amount of offloading data to the MEC server and/or the FAAS, and the novel concept of Satisfaction Equilibrium (SE) is introduced where the IP cameras satisfy their minimum QoS prerequisites instead of maximizing their performance by consuming additional system resources. A distributed learning algorithm determines the IP cameras\u27 stable data offloading. Also, a reinforcement learning algorithm indicates the FAAS\u27s movement among the AoIs exploiting the accuracy, timeliness, and certainty of the collected data by the IP cameras per AoI. Detailed numerical and comparative results are presented to show the operation and efficiency of the proposed framework

Class-G Headphone Amplifier Architectures

To maximize the battery life of portable audio devices like iPods, MP3 players and mobile phones, there is a need for audio power amplifiers with low quiescent power, high efficiency along with uncompromising quality (Distortion performance/ THD) and low cost. Despite their high efficiency, Class-D amplifiers are undesirable as headphone drivers in mobile devices, owing to their high EMI radiation, additional costs due to filtering required at the output and also their poor linearity at small signal levels. Almost all of todays headphone drivers are Class-AB linear amplifiers, with poor efficiencies. Here we propose a Class-G linear amplifier, which uses rail switching to improve efficiency. It can be viewed as a Class-AB amplifier operating from the lower supply and a Class-C amplifier from the higher supply. Though the classical definition of efficiency using full-scale sine wave does not show much improvement for Class-G (85.9 percent) over Class-AB (78 percent), we demonstrate that the Class-G audio amplifiers can have significant improvement of efficiencies (battery life) in the practical sense. By considering the amplitude distribution of audio signals a new realistic definition of efficiency has been proposed. This definition helps in demonstrating the advantage of using Class-G over Class-AB and also helps in optimizing the choice of supply voltages which is critical to maximizing the efficiency of Class-G amplifiers. Two new circuit topologies have been proposed and thoroughly investigated. The first circuit is more like a developmental stage and is designed/fabricated in AMI 0.5um. The second proposed Class-G amplifier with modified Class-AB bias, implemented in IBM 90nm, achieves -82.5dB THD N by seamless supply switching and uses the least reported quiescent power (350 mu W) and area (0.08mm^2)