FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch Generation

We propose FPGA-Patch, the first-of-its-kind defense that leverages automated program repair concepts to thwart power side-channel attacks on cloud FPGAs. FPGA-Patch generates isofunctional variants of the target hardware by injecting faults and finding transformations that eliminate failure. The obtained variants display different hardware characteristics, ensuring a maximal diversity in power traces once dynamically swapped at run-time. Yet, FPGA-Patch forces the variants to have enough similarity, enabling bitstream compression and minimizing dynamic exchange costs. Considering AES running on AMD/Xilinx FPGA, FPGA-Patch increases the attacker's effort by three orders of magnitude, while preserving the performance of AES and a minimal area overhead of 14.2%.Comment: 6 page

Digital Circuit Design Using Floating Gate Transistors

Floating gate (flash) transistors are used exclusively for memory applications today. These applications include SD cards of various form factors, USB flash drives and SSDs. In this thesis, we explore the use of flash transistors to implement digital logic circuits. Since the threshold voltage of flash transistors can be modified at a fine granularity during programming, several advantages are obtained by our flash-based digital circuit design approach. For one, speed binning at the factory can be controlled with precision. Secondly, an IC can be re-programmed in the field, to negate effects such as aging, which has been a significant problem in recent times, particularly for mission-critical applications. Thirdly, unlike a regular MOSFET, which has one threshold voltage level, a flash transistor can have multiple threshold voltage levels. The benefit of having multiple threshold voltage levels in a flash transistor is that it allows the ability to encode more symbols in each device, unlike a regular MOSFET. This allows us to implement multi-valued logic functions natively. In this thesis, we evaluate different flash-based digital circuit design approaches and compare their performance with a traditional CMOS standard cell-based design approach. We begin by evaluating our design approach at the cell level to optimize the design’s delay, power energy and physical area characteristics. The flash-based approach is demonstrated to be better than the CMOS standard cell approach, for these performance metrics. Afterwards, we present the performance of our design approach at the block level. We describe a synthesis flow to decompose a circuit block into a network of interconnected flash-based circuit cells. We also describe techniques to optimize the resulting network of flash-based circuit cells using don’t cares. Our optimization approach distinguishes itself from other optimization techniques that use don’t cares, since it a) targets a flash-based design flow, b) optimizes clusters of logic nodes at once instead of one node at a time, c) attempts to reduce the number of cubes instead of reducing the number of literals in each cube and d) performs optimization on the post-technology mapped netlist which results in a direct improvement in result quality, as compared to pre-technology mapping logic optimization that is typically done in the literature. The resulting network characteristics (delay, power, energy and physical area) are presented. These results are compared with a standard cell-based realization of the same block (obtained using commercial tools) and we demonstrate significant improvements in all the design metrics. We also study flash-based FPGA designs (both static and dynamic), and present the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished, for all the proposed designs

Digital Circuit Design Using Floating Gate Transistors

Floating gate (flash) transistors are used exclusively for memory applications today. These applications include SD cards of various form factors, USB flash drives and SSDs. In this thesis, we explore the use of flash transistors to implement digital logic circuits. Since the threshold voltage of flash transistors can be modified at a fine granularity during programming, several advantages are obtained by our flash-based digital circuit design approach. For one, speed binning at the factory can be controlled with precision. Secondly, an IC can be re-programmed in the field, to negate effects such as aging, which has been a significant problem in recent times, particularly for mission-critical applications. Thirdly, unlike a regular MOSFET, which has one threshold voltage level, a flash transistor can have multiple threshold voltage levels. The benefit of having multiple threshold voltage levels in a flash transistor is that it allows the ability to encode more symbols in each device, unlike a regular MOSFET. This allows us to implement multi-valued logic functions natively. In this thesis, we evaluate different flash-based digital circuit design approaches and compare their performance with a traditional CMOS standard cell-based design approach. We begin by evaluating our design approach at the cell level to optimize the design’s delay, power energy and physical area characteristics. The flash-based approach is demonstrated to be better than the CMOS standard cell approach, for these performance metrics. Afterwards, we present the performance of our design approach at the block level. We describe a synthesis flow to decompose a circuit block into a network of interconnected flash-based circuit cells. We also describe techniques to optimize the resulting network of flash-based circuit cells using don’t cares. Our optimization approach distinguishes itself from other optimization techniques that use don’t cares, since it a) targets a flash-based design flow, b) optimizes clusters of logic nodes at once instead of one node at a time, c) attempts to reduce the number of cubes instead of reducing the number of literals in each cube and d) performs optimization on the post-technology mapped netlist which results in a direct improvement in result quality, as compared to pre-technology mapping logic optimization that is typically done in the literature. The resulting network characteristics (delay, power, energy and physical area) are presented. These results are compared with a standard cell-based realization of the same block (obtained using commercial tools) and we demonstrate significant improvements in all the design metrics. We also study flash-based FPGA designs (both static and dynamic), and present the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished, for all the proposed designs

Autoenfoque en imagen ultrasónica

La inspección de componentes por ultrasonidos se realiza, actualmente, con sistemas de imagen phased array, versión industrial de los ecógrafos médicos. En ambos casos se utiliza un array con decenas o centenares de pequeños transductores piezoeléctricos que se controlan individualmente para enfocar y deflectar el haz ultrasónico en emisión y recepción. Pero, mientras que en medicina el array está en contacto con el cuerpo, que es flexible, en la industria se suele interponer un medio acoplante entre el array y el componente a inspeccionar. Cuando la geometría de la pieza no es plana se utiliza agua como medio acoplante, que se adapta a la forma de la pieza y proporciona un medio continuo y de baja atenuación para la transmisión del sonido. En estas condiciones existen dos medios de propagación, lo que dificulta la determinación de los retardos de enfoque por efectos de la refracción. Como en estas condiciones no existen fórmulas cerradas que faciliten su cálculo, hasta la fecha se han venido utilizando procesos iterativos computacionalmente costosos que impiden la modificación rápida del enfoque cuando varía la geometría de la pieza (por ejemplo, durante la realización de un barrido). Estas razones han impedido el desarrollo de técnicas de autoenfoque efectivas. Esta Tesis aporta tres técnicas que, junto al cálculo en tiempo real de los parámetros de enfoque y un soporte arquitectural de imagen a ultra-alta velocidad, están entre las primeras aproximaciones reales para solucionar el problema del autoenfoque en imagen ultrasónica. De hecho, una de ellas (AUTOFOCUS) ha sido patentada y transferida a la industria, que la comercializa en equipos phased array con esta capacidad. La memoria describe las motivaciones, fundamentos, aproximaciones conocidas al problema así como las dificultades y las soluciones investigadas. Una segunda parte incluye las publicaciones más relevantes donde se han comunicado los resultados, contrastando los teóricamente esperados con los experimentalmente obtenidos

Field-Programmable Gate Arrays in Nuclear Power Plant Safety Automation

Kenttäohjelmoitava porttimatriisi (FPGA) -tekniikasta on tulossa yhä yleisempi ydinvoimaloiden instrumentointi- ja säätöjärjestelmissä. Nykyään FPGA-tekniikkaa on alettu käyttää jo kaikkein kriittisimmissäkin turvajärjestelmissä. FPGA on digitaalinen puolijohdetekniikkaan perustuva mikropiiri, jota voi käyttää esimerkiksi korvaamaan mikroprosessoripohjaisia ohjelmistoteknisiä järjestelmiä, joiden kanssa on tällä hetkellä ongelmia muun muassa turvallisuuden ja toimivuuden osoittamisessa. FPGA-sovelluksella pystytään lähes kaikkeen samaan kuin ohjelmistosovelluksella, mutta se on yksinkertaisempi ja täten väitetysti helpompi kelpoistaa eli osoittaa sen toimivuus. FPGA-tekniikalle ei kuitenkaan ole vielä ydinvoima-alalla kansainvälisesti hyväksyttyjä ja yhdenmukaisia ohjeistuksia ja standardeja, jotka ottaisivat kantaa siihen, mitä kaikkea FPGA-pohjaisten sovellusten kelpoistaminen ja lisensiointi vaatii. Tässä diplomityössä esitellään ensin FPGA-tekniikka yleisesti. Esittelyssä käydään muun muassa läpi eri lähteistä yhdistetyt FPGA-sovellusten suunnittelu- ja V&V prosessit. Eräs työn tavoitteista on löytää näihin prosesseihin liittyvät parhaat toimintatavat. Yleisesittelyn jälkeen käydään läpi nykyiset sovellukset, hyödyt ja haitat, sekä muut FPGA-tekniikan käyttöön ydinvoimaloiden turva-automaatiossa liittyvät asiat. Samassa yhteydessä tehdään vertailu FPGA- ja mikroprosessori-tekniikan välillä, jotta voitaisiin tunnustaa FPGA:n edut mikroprosessoriin verrattuna. Lopuksi diplomityössä esitellään case-tutkimus, jossa toteutetaan yksi kuvitteellinen mutta realistinen turva-automaatiojärjestelmä käyttäen kahta FPGA-laitetta. Case-tutkimuksen tarkoituksena on kokeilla eri suunnittelu- ja V&V-menetelmiä, jotka löydettiin kirjallisuudesta, ja saada käytännön kokemusta FPGA-sovellusten suunnittelusta ja V&V:stä.The field-programmable gate array (FPGA) technology is becoming increasingly common in the instrumentation and control (I&C) systems of nuclear power plants (NPPs). The technology is now being adopted even in the most safety-critical systems. An FPGA is a digital semiconductor device that can be used as a replacement for the current microprocessor-based software systems with which there are problems e.g. in safety justification. An FPGA application has practically the same capabilities as a software application but is less complex and thus arguably easier to qualify. However, the FPGA is still rather new in the nuclear power industry and thus there are no consistent and harmonised international guidance and standards regarding how to design and license FPGAs for NPP safety automation applications. In this thesis, a general overview of the FPGA technology is first given. The activities in the different phases of the FPGA design and verification and validation (V&V) processes are defined based on processes found in various different sources with the intent to identify best practices for said processes. After the general overview, the current applications, advantages and disadvantages, and other aspects related to FPGAs in NPP safety automation are looked into. A comparison with microprocessor-based systems is also done in order to recognise the perceived benefits of using FPGAs instead of microprocessors. Finally, a case study is presented. In the case study, a fictional but realistic safety automation application is implemented using two FPGA devices. The objectives of the case study are to try out the different design and V&V methods found in the literature, and to get hands-on experience on the FPGA application development and V&V

Generation of Application Specific Hardware Extensions for Hybrid Architectures: The Development of PIRANHA - A GCC Plugin for High-Level-Synthesis

Architectures combining a field programmable gate array (FPGA) and a general-purpose processor on a single chip became increasingly popular in recent years. On the one hand, such hybrid architectures facilitate the use of application specific hardware accelerators that improve the performance of the software on the host processor. On the other hand, it obliges system designers to handle the whole process of hardware/software co-design. The complexity of this process is still one of the main reasons, that hinders the widespread use of hybrid architectures. Thus, an automated process that aids programmers with the hardware/software partitioning and the generation of application specific accelerators is an important issue. The method presented in this thesis neither requires restrictions of the used high-level-language nor special source code annotations. Usually, this is an entry barrier for programmers without deeper understanding of the underlying hardware platform. This thesis introduces a seamless programming flow that allows generating hardware accelerators for unrestricted, legacy C code. The implementation consists of a GCC plugin that automatically identifies application hot-spots and generates hardware accelerators accordingly. Apart from the accelerator implementation in a hardware description language, the compiler plugin provides the generation of a host processor interfaces and, if necessary, a prototypical integration with the host operating system. An evaluation with typical embedded applications shows general benefits of the approach, but also reveals limiting factors that hamper possible performance improvements

Towards a Secure and Reliable System

Abstract. In this article we describe a system based on a 32-bit processor, Leon, complete with security features offered by a specific cryptographic AES IP. Hardening is done not only on the principal hardware components but on the operating system as well, with attention for possible interaction between the different levels. The cryptographic IP is protected too to offer good resistance against, for example, fault-based attacks

Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip 2010 - ReCoSoC\u2710 - May 17-19, 2010 Karlsruhe, Germany. (KIT Scientific Reports ; 7551)

ReCoSoC is intended to be a periodic annual meeting to expose and discuss gathered expertise as well as state of the art research around SoC related topics through plenary invited papers and posters. The workshop aims to provide a prospective view of tomorrow\u27s challenges in the multibillion transistor era, taking into account the emerging techniques and architectures exploring the synergy between flexible on-chip communication and system reconfigurability

VThreads: A novel VLIW chip multiprocessor with hardware-assisted PThreads

We discuss VThreads, a novel VLIW CMP with hardware-assisted shared-memory Thread support. VThreads supports Instruction Level Parallelism via static multiple-issue and Thread Level Parallelism via hardware-assisted POSIX Threads along with extensive customization. It allows the instantiation of tightlycoupled streaming accelerators and supports up to 7-address Multiple-Input, Multiple-Output instruction extensions. VThreads is designed in technology-independent Register-Transfer-Level VHDL and prototyped on 40 nm and 28 nm Field-Programmable gate arrays. It was evaluated against a PThreads-based multiprocessor based on the Sparc-V8 ISA. On a 65 nm ASIC implementation VThreads achieves up to x7.2 performance increase on synthetic benchmarks, x5 on a parallel Mandelbrot implementation, 66% better on a threaded JPEG implementation, 79% better on an edge-detection benchmark and ~13% improvement on DES compared to the Leon3MP CMP. In the range of 2 to 8 cores VThreads demonstrates a post-route (statistical) power reduction between 65% to 57% at an area increase of 1.2%-10% for 1-8 cores, compared to a similarly-configured Leon3MP CMP. This combination of micro-architectural features, scalability, extensibility, hardware support for low-latency PThreads, power efficiency and area make the processor an attractive proposition for low-power, deeply-embedded applications requiring minimum OS support