A Router for Symmetrical FPGAs based on Exact Routing Density Evaluation

Abstract This paper presents a new performance and routability driven routing algorithm for symmetrical array based field-programmable gate arrays (FPGAs). A key contribution of our work is to overcome one essential limitation of the previous routing algorithms: inaccurate estimations of routing density which were too general for symmetrical FPGAs. To this end, we derive an exact routing density calculation that is based on a precise analysis of the structure (switch block) of symmetrical FPGAs, and utilize it consistently in global and detailed routings. With an introduction of the proposed accurate routing metrics, we design a new routing algorithm called a cost-effective net-decomposition based routing which is fast, and yet produces remarkable routing results in terms of both routability and path/net delays. We performed an extensive experiment to show the effectiveness of our algorithm based on the proposed cost metrics

Delay Measurements and Self Characterisation on FPGAs

This thesis examines new timing measurement methods for self delay characterisation of Field-Programmable Gate Arrays (FPGAs) components and delay measurement of complex circuits on FPGAs. Two novel measurement techniques based on analysis of a circuit's output failure rate and transition probability is proposed for accurate, precise and efficient measurement of propagation delays. The transition probability based method is especially attractive, since it requires no modifications in the circuit-under-test and requires little hardware resources, making it an ideal method for physical delay analysis of FPGA circuits. The relentless advancements in process technology has led to smaller and denser transistors in integrated circuits. While FPGA users benefit from this in terms of increased hardware resources for more complex designs, the actual productivity with FPGA in terms of timing performance (operating frequency, latency and throughput) has lagged behind the potential improvements from the improved technology due to delay variability in FPGA components and the inaccuracy of timing models used in FPGA timing analysis. The ability to measure delay of any arbitrary circuit on FPGA offers many opportunities for on-chip characterisation and physical timing analysis, allowing delay variability to be accurately tracked and variation-aware optimisations to be developed, reducing the productivity gap observed in today's FPGA designs. The measurement techniques are developed into complete self measurement and characterisation platforms in this thesis, demonstrating their practical uses in actual FPGA hardware for cross-chip delay characterisation and accurate delay measurement of both complex combinatorial and sequential circuits, further reinforcing their positions in solving the delay variability problem in FPGAs

The Level-0 Muon Trigger for the LHCb Experiment

A very compact architecture has been developed for the first level Muon Trigger of the LHCb experiment that processes 40 millions of proton-proton collisions per second. For each collision, it receives 3.2 kBytes of data and it finds straight tracks within a 1.2 microseconds latency. The trigger implementation is massively parallel, pipelined and fully synchronous with the LHC clock. It relies on 248 high density Field Programable Gate arrays and on the massive use of multigigabit serial link transceivers embedded inside FPGAs.Comment: 33 pages, 16 figures, submitted to NIM

Connection-switch box design and optimal MST-based graph algorithm on FPGA segmentation design.

Zhou Lin.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 50-53).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Aims and Contribution --- p.3Chapter 1.3 --- Thesis Overview --- p.4Chapter 2 --- Field-Programmable Gate Array and Routing Algorithm in VPR --- p.6Chapter 2.1 --- Commercially Available FPGAs --- p.6Chapter 2.2 --- FPGA Logic Block Architecture --- p.7Chapter 2.2.1 --- Logic Block Functionality vs. FPGA Area-Efficiency --- p.7Chapter 2.2.2 --- Logic Block Functionality vs. FPGA Delay-Performance --- p.7Chapter 2.2.3 --- Lookup Table-Based FPGAs --- p.8Chapter 2.3 --- FPGA Routing Architecture --- p.8Chapter 2.4 --- Design Parameters of FPGA Routing Architecture --- p.10Chapter 2.5 --- CAD for FPGAs --- p.10Chapter 2.5.1 --- Synthesis and Logic Block Packing --- p.11Chapter 2.5.2 --- Placement --- p.11Chapter 2.5.3 --- Routing --- p.12Chapter 2.5.4 --- Delay Modelling --- p.13Chapter 2.5.5 --- Timing Analysis --- p.13Chapter 2.6 --- FPGA Programming Technologies --- p.13Chapter 2.7 --- Routing Algorithm in VPR --- p.14Chapter 2.7.1 --- Pathfinder Negotiated Congestion Algorithm --- p.14Chapter 2.7.2 --- Routing Algorithm Used by VPR --- p.16Chapter 3 --- Connection-Switch Box Design --- p.17Chapter 3.1 --- Introduction --- p.17Chapter 3.2 --- Connection-Switch Box Design Algorithm --- p.19Chapter 3.2.1 --- Connection between Logic Pins and Tracks --- p.20Chapter 3.2.2 --- Connection between Pad Pins and Tracks --- p.25Chapter 3.3 --- Switch Number Comparisons --- p.26Chapter 3.4 --- Experimental Results --- p.29Chapter 3.5 --- Summary --- p.32Chapter 4 --- Optimal MST-Based Graph Algorithm on FPGA Segmenta- tion Design --- p.37Chapter 4.1 --- Introduction --- p.37Chapter 4.2 --- MST-Based Graph Algorithm on FPGA Channel Segmentation Design --- p.39Chapter 4.2.1 --- Net Merging Problem of Row-Based FPGAs --- p.41Chapter 4.2.2 --- Extended Net Merging Problem of Symmetrical Array FPGAs --- p.44Chapter 4.3 --- Experimental Results --- p.46Chapter 4.4 --- Summary --- p.46Chapter 5 --- Conclusions --- p.48Bibliography --- p.5

High-Performance Fpaa Design For Hierarchical Implementation Of Analog And Mixed-Signal Systems

The design complexity of today's IC has increased dramatically due to the high integration allowed by advanced CMOS VLSI process. A key to manage the increased design complexity while meeting the shortening time-to-market is design automation. In digital world, the field-programmable gate arrays (FPGAs) have evolved to play a very important role by providing ASIC-compatible design methodologies that include design-for-testability, design optimization and rapid prototyping. On the analog side, the drive towards shorter design cycles has demanded the development of high performance analog circuits that are configurable and suitable for CAD methodologies. Field-programmable analog arrays (FPAAs) are intended to achieve the benefits for analog system design as FPGAs have in the digital field. Despite of the obvious advantages of hierarchical analog design, namely short time-to-market and low non-recurring engineering (NRE) costs, this approach has some apparent disadvantages. The redundant devices and routing resources for programmability requires extra chip area, while switch and interconnect parasitics cause considerable performance degradation. To deliver a high-performance FPAA, effective methodologies must be developed to minimize those adversary effects. In this dissertation, three important aspects in the FPAA design are studied to achieve that goal: the programming technology, the configurable analog block (CAB) design and the routing architecture design. Enabled by the Laser MakelinkTM technology, which provides nearly ideal programmable switches, channel segmentation algorithms are developed to improve channel routability and reduce interconnect parasitics. Segmented routing are studied and performance metrics accounting for interconnect parasitics are proposed for performance-driven analog routing. For large scale arrays, buffer insertions are considered to further reduce interconnection delay and cross-coupling noise. A high-performance, highly flexible CAB is developed to realized both continuous-mode and switched-capacitor circuits. In the end, the implementation of an 8-bit, 50MSPS pipelined A/D converter using the proposed FPAA is presented as an example of the hierarchical analog design approach, with its key performance specifications discussed

Programmable flexible cores for SoC applications

Tese de mestrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 200