Future benefits and applications of intelligent on-board processing to VSAT services

The trends and roles of VSAT services in the year 2010 time frame are examined based on an overall network and service model for that period. An estimate of the VSAT traffic is then made and the service and general network requirements are identified. In order to accommodate these traffic needs, four satellite VSAT architectures based on the use of fixed or scanning multibeam antennas in conjunction with IF switching or onboard regeneration and baseband processing are suggested. The performance of each of these architectures is assessed and the key enabling technologies are identified

Flexible structure control laboratory development and technology demonstration

An experimental structure is described which was constructed to demonstrate and validate recent emerging technologies in the active control and identification of large flexible space structures. The configuration consists of a large, 20 foot diameter antenna-like flexible structure in the horizontal plane with a gimballed central hub, a flexible feed-boom assembly hanging from the hub, and 12 flexible ribs radiating outward. Fourteen electrodynamic force actuators mounted to the hub and to the individual ribs provide the means to excite the structure and exert control forces. Thirty permanently mounted sensors, including optical encoders and analog induction devices provide measurements of structural response at widely distributed points. An experimental remote optical sensor provides sixteen additional sensing channels. A computer samples the sensors, computes the control updates and sends commands to the actuators in real time, while simultaneously displaying selected outputs on a graphics terminal and saving them in memory. Several control experiments were conducted thus far and are documented. These include implementation of distributed parameter system control, model reference adaptive control, and static shape control. These experiments have demonstrated the successful implementation of state-of-the-art control approaches using actual hardware

The 30/20 GHz flight experiment system, phase 2. Volume 2: Experiment system description

A detailed technical description of the 30/20 GHz flight experiment system is presented. The overall communication system is described with performance analyses, communication operations, and experiment plans. Hardware descriptions of the payload are given with the tradeoff studies that led to the final design. The spacecraft bus which carries the payload is discussed and its interface with the launch vehicle system is described. Finally, the hardwares and the operations of the terrestrial segment are presented

Design of an integrated airframe/propulsion control system architecture

The design of an integrated airframe/propulsion control system architecture is described. The design is based on a prevalidation methodology that uses both reliability and performance. A detailed account is given for the testing associated with a subset of the architecture and concludes with general observations of applying the methodology to the architecture

Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated

Modeling of the northern hemisphere ice sheets during the last glacial cycle and glaciological sensitivity

We present a new three-dimensional thermomechanically coupled ice sheet model of the northern hemisphere to reconstruct the Quaternary ice sheets during the last glacial cycle. The model includes basal sliding, internal representations of the surface mass balance, glacial isostasy, and a treatment for marine calving. The time dependent forcing consists of temperature and precipitation anomalies from the UKMO GCM scaled to the GRIP ice core ∂18O record. Model parameters were chosen to best match geomorphological inferences on maximum LGM extent and global eustatic sea level change. For our standard run we find a maximum ice volume of 57 x 106 km3 at 18.5 ka cal BP. This corresponds to a eustatic sea level lowering of 110 m after correction for hydro-isostatic displacement and anomalous ice resulting from defects in the PMIP climatic forcing. Of this 110 m, 82 m was stored in the North American ice sheet and 25 m in the Eurasian ice sheet. We determine the qualitative and quantitative response of the model from a comprehensive sensitivity study in which the most important parameters were varied over their respective ranges of uncertainty. Model outputs comparable to the observational record were explored in detail as a linear function along the axes of parameter space of the reference model. The method reveals the dominance of climate uncertainty when modelling the LGM configuration of the northern hemisphere ice sheets, but also highlights the role of ice rheology and basal processes for aspect ratio, and glacial isostasy and calving for the timing of maximum ice volume

Planning assistance for the NASA 30/20 GHz program. Network control architecture study.

Network Control Architecture for a 30/20 GHz flight experiment system operating in the Time Division Multiple Access (TDMA) was studied. Architecture development, identification of processing functions, and performance requirements for the Master Control Station (MCS), diversity trunking stations, and Customer Premises Service (CPS) stations are covered. Preliminary hardware and software processing requirements as well as budgetary cost estimates for the network control system are given. For the trunking system control, areas covered include on board SS-TDMA switch organization, frame structure, acquisition and synchronization, channel assignment, fade detection and adaptive power control, on board oscillator control, and terrestrial network timing. For the CPS control, they include on board processing and adaptive forward error correction control

The 30/20 GHz flight experiment system, phase 2. Volume 1: Executive summary

Summary information on the final communication system design, communication payload, space vehicle, and development plan for the 30/20 GHz flight experiment will be installed on the LEASAT spacecraft which will be placed into orbit from the space shuttle cargo bay. The communication concept has two parts: a truck service and a customer premise service (CPS). The trucking system serves four spot beams which are interconnected in a satellite switched time division multiple access mode by an IF switch matrix. The CPS covers two large areas of the eastern United States with a pair of scanning beams

3중 샘플링 방식 델타-시그마 ADC를 이용한 디지털 Capacitive MEMS 마이크로폰

학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 김수환.본 논문에서는 트리플 샘플링 적분기를 사용한 Capacitive 방식의 MEMS 마이크로폰이 제시되었다. 트리플 샘플링은 델타-시그마 방식의 아날로그-디지털 변환기의 첫 번째 적분기에 사용되었고 크게 두 가지의 동작으로 구분된다. 첫 번째로 적분기의 입력에서 반주기 지연 차동 입력을 빼서 신호 크기를 2배로 만들는 방식. 두 번째로 DAC의 피드백 커패시터를 샘플링 커패시터로 사용하여 입력 전압을 추가로 증가시키는 방식이다. 추가적으로 기존에서 샘플링 커패시터를 증가시켜 신호의 크기를 증폭시키는 방식과 결합하여 실수배의 이득을 얻을 수 있다. 또한 추가적인 커패시터, 타이밍, 전류 소모 없이 구조 변경만으로 이를 달성하였기 때문에 별다른 trade-off 없이 신호의 크기를 증폭시킬 수 있었다. 추가적으로 트리플 샘플링 방식의 적분기 신호 전달 함수 및 잡음 분석 또한 포함하였다. 우리의 readout 회로는 공급 전압이 1.8V인 0.18 m CMOS 공정으로 구현하였고 single-ended capacitive MEMS 트랜스듀서를 사용하여 측정하였다. 전류 소모량은 520 μA 이다. 마이크로폰은 A-weighted 신호 대 잡음 비는 62.1 dBA, 음향 과부하 지점은 115 dB SPL을 달성하였고 칩의 die size는 0.98〖"mm" 〗^2 이다.A triple-sampling ΔΣ ADC can replace the programmable-gain amplifier commonly used in the readout circuit for a digital capacitive MEMS microphone. The input voltage can then be multiplied by subtracting a further half-period delayed differential input and using the feedback capacitor of the DAC as a sampling capacitor. This triple-sampling technique results in a readout circuit with sensitivity and noise performance comparable to recent designs, but with a reduced power requirement. CMRR improvement is achieved by subtracting differential inputs and superior noise performance compare to conventional structure, as amplifier noise and DAC kT/C noise is not amplified by triple-sampling structure while the signal is increased by its gain. Triple-sampling also can be operated as a single-to-differential circuit. A MEMS microphone incorporating this readout circuit, fabricated in a 0.18μm CMOS process, achieved an A-weighted SNR of 62.1 dBA at 94 dB SPL with 520 μA current consumption, to which triple-sampling was shown to contribute 4.5 dBA.CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.1.1 MEMS MICROPHONE TRENDS 1 1.1.2 TYPE OF MEMS MICROPHONES 4 1.1.3 PREVIOUS WORKS 7 1.2 MEMS MICROPHONE BASIC TERMS 9 1.3 THESIS ORGANIZATION 12 CHAPTER 2 SYSTEM OVERVIEW 13 2.1 SYSTEM ARCHITECTURE 13 CHAPTER 3 INTERFACE CIRCUITS AND POWER MANAGEMENT CIRCUITS 16 3.1 PSEUDO-DIFFERENTIAL SOURCE FOLLOWER 17 3.2 CHARGE PUMP 19 3.3 LOW DROPOUT REGULATOR 22 3.3.1 DESIGN CONSIDERATION OF LOW DROPOUT REGULATOR 22 3.3.2 IMPLEMENTATION OF LOW DROPOUT REGULATOR 26 CHAPTER 4 TRIPLE-SAMPLING DELTA-SIGMA ADC 31 4.1 BASIC OF DELTA-SIGMA ADC 31 4.2 IMPLEMENTATION OF TRIPLE-SAMPLING DELTA-SIGMA MODULATOR 37 4.2.1 CONVENTIONAL 1ST INTEGRATOR STRUCTURE 37 4.2.2 CROSS-SAMPLING 1ST INTEGRATOR 40 4.2.3 TRIPLE-SAMPLING 1ST INTEGRATOR 43 4.2.4 STF ANALYSIS OF TRIPLE-SAMPLING 1ST INTEGRATOR 47 4.2.5 THERMAL NOISE ANALYSIS OF TRIPLE-SAMPLING 1ST INTEGRATOR 51 4.2 CIRCUIT IMPLEMENTATION OF DELTA-SIGMA ADC 57 CHAPTER 5 MEASUREMENT RESULTS 64 5.1 MEASUREMENT ENVIRONMENT 64 5.2 MEASUREMENT RESULTS 67 5.3 PERFORMANCE SUMMARY 72 CHAPTER 6 CONCLUSION 74 BIBLIOGRAPHY 76 한글초록 79박