One-Dimensional Multi-Subband Monte Carlo Simulation of Charge Transport in Si Nanowire Transistors

In this paper, we employ a newly-developed one-dimensional multi-subband Monte Carlo (1DMSMC) simulation module to study electron transport in nanowire structures. The 1DMSMC simulation module is integrated into the GSS TCAD simulator GARAND coupling a MC electron trajectory simulation with a 3D Poisson-2D Schrödinger solver, and accounting for the modified acoustic phonon, optical phonon, and surface roughness scattering mechanisms. We apply the simulator to investigate the effect of the overlap factor, scattering mechanisms, material and geometrical properties on the mobility in silicon nanowire field-effect transistors (NWTs). This paper emphasizes the importance of using 1D models that include correctly quantum confinement and allow for a reliable prediction of the performance of NWTs at the scaling limits. Our simulator is a valuable tool for providing optimal designs for ultra-scaled NWTs, in terms of performance and reliability

Quantum Enhancement of a S/D Tunneling Model in a 2D MS-EMC Nanodevice Simulator: NEGF Comparison and Impact of Effective Mass Variation

As complementary metal-oxide-semiconductor (CMOS) transistors approach the nanometer scale, it has become mandatory to incorporate suitable quantum formalism into electron transport simulators. In this work, we present the quantum enhancement of a 2D Multi-Subband Ensemble Monte Carlo (MS-EMC) simulator, which includes a novel module for the direct Source-to-Drain tunneling (S/D tunneling), and its verification in the simulation of Double-Gate Silicon-On-Insulator (DGSOI) transistors and FinFETs. Compared to ballistic Non-Equilibrium Green’s Function (NEGF) simulations, our results show accurate I D vs. V GS and subthreshold characteristics for both devices. Besides, we investigate the impact of the effective masses extracted Density Functional Theory (DFT) simulations, showing that they are the key of not only the general thermionic emission behavior of simulated devices, but also the electron probability of experiencing tunneling phenomena.This project has received funding from EPSRC UKRI Innovation Fellowship scheme under grant agreement No. EP/S001131/1 (QSEE) and No. EP/P009972/1 (QUANTDEVMOD)

Multi-Subband Ensemble Monte Carlo simulations of scaled GAA MOSFETs

We developed a Multi-Subband Ensemble Monte Carlo simulator for non-planar devices, taking into account two-dimensional quantum confinement. It couples self-consistently the solution of the 3D Poisson equation, the 2D Schrödinger equation, and the 1D Boltzmann transport equation with the Ensemble Monte Carlo method. This simulator was employed to study MOS devices based on ultra-scaled Gate-All-Around Si nanowires with diameters in the range from 4 nm to 8 nm with gate length from 8 nm to 14 nm. We studied the output and transfer characteristics, interpreting the behavior in the sub-threshold region and in the ON state in terms of the spatial charge distribution and the mobility computed with the same simulator. We analyzed the results, highlighting the contribution of different valleys and subbands and the effect of the gate bias on the energy and velocity profiles. Finally the scaling behavior was studied, showing that only the devices with D = 4 nm maintain a good control of the short channel effects down to the gate length of 8 nm

Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit

In this work we investigate the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future CMOS applications at the scaling limit. For the purpose of this paper, we created Si NWTs with two channel crystallographic orientations <110> and <100> and six different cross-section profiles. In the first part, we study the impact of quantum corrections on the gate capacitance and mobile charge in the channel. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic performance of the NWTs, is also investigated. The influence of the rotating of the NWTs cross-sectional geometry by 90o on charge distribution in the channel is also studied. We compare the correlation between the charge profile in the channel and cross-sectional dimension for circular transistor with four different cross-sections diameters: 5nm, 6nm, 7nm and 8nm. In the second part of this paper, we expand the computational study by including different gate lengths for some of the Si NWTs. As a result, we establish a correlation between the mobile charge distribution in the channel and the gate capacitance, drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All calculations are based on a quantum mechanical description of the mobile charge distribution in the channel. This description is based on the solution of the Schrödinger equation in NWT cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions

Impact of the technology boosters on the MOSFET performance

The understanding of the charge transport in nano-scale CMOS device is a very challenging issue that requires a physics-based modelling approach. I use a Multi Subband Monte Carlo simulation framework to assess the effects of some of the mostly used techniques to overcome the performances of the conventional ultra-scaled MOSFET

Simulation and Modeling of Novel Electronic Device Architectures with NESS (Nano-Electronic Simulation Software): A Modular Nano TCAD Simulation Framework

The modeling of nano-electronic devices is a cost-effective approach for optimizing the semiconductor device performance and for guiding the fabrication technology. In this paper, we present the capabilities of the new flexible multi-scale nano TCAD simulation software called NanoElectronic Simulation Software (NESS). NESS is designed to study the charge transport in contemporary and novel ultra-scaled semiconductor devices. In order to simulate the charge transport in such ultra-scaled devices with complex architectures and design, we have developed numerous simulation modules based on various simulation approaches. Currently, NESS contains a driftdiffusion, Kubo–Greenwood, and non-equilibrium Green’s function (NEGF) modules. All modules are numerical solvers which are implemented in the C++ programming language, and all of them are linked and solved self-consistently with the Poisson equation. Here, we have deployed some of those modules to showcase the capabilities of NESS to simulate advanced nano-scale semiconductor devices. The devices simulated in this paper are chosen to represent the current state-of-the-art and future technologies where quantum mechanical effects play an important role. Our examples include ultra-scaled nanowire transistors, tunnel transistors, resonant tunneling diodes, and negative capacitance transistors. Our results show that NESS is a robust, fast, and reliable simulation platform which can accurately predict and describe the underlying physics in novel ultra-scaled electronic devices.European Union Horizon 2020 - 688101 SUPERAID7EPSRC UKRI Innovation Fellowship - EP/S001131/1 (QSEE), No. EP/P009972/1 (QUANTDEVMOD)H2020-FETOPEN-2019 s- No.862539-Electromed-FET OPEN.No. EP/S000259/1(Variability PDK for design based research on FPGA/neuro computing

Advanced III-V / Si nano-scale transistors and contacts: Modeling and analysis

The exponential miniaturization of Si CMOS technology has been a key to the electronics revolution. However, the continuous downscaling of the gate length becomes the biggest challenge to maintain higher speed, lower power, and better electrostatic integrity for each following generation. Hence, novel devices and better channel materials than Si are considered to improve the metal-oxide-semiconductor field-effect transistors (MOSFETs) device performance. III-V compound semiconductors and multi-gate structures are being considered as promising candidates in the next CMOS technology. III-V and Si nano-scale transistors in different architectures are investigated (1) to compare the performance between InGaAs of III-V compound semiconductors and strained-Si in planar FETs and triple-gate non-planar FinFETs. (2) to demonstrate whether or not these technologies are viable alternatives to Si and conventional planar FETs. The simulation results indicate that III-V FETs do not outperform Si FETs in the ballistic transport regime, and triple-gate FinFETs surely represent the best architecture for sub-15nm gate contacts, independently from the choice of channel material. ^ This work also proves that the contact resistance becomes a limiting factor of device performance as it takes larger fraction of the total on-state resistance. Hence, contact resistance must be reduced to meet the next ITRS requirements. However, from a modeling point of view, the understanding of the contacts still remains limited due to its size and multiple associated scattering effects, while the intrinsic device performance can be projected. Therefore, a precise theoretical modeling is required to advance optimized contact design to improve overall device performance. In this work, various factors of the contact resistances are investigated within realistic contact-to-channel structure of III-V quantum well field-effect transistors (QWFET). The key finding is that the contact-to-channel resistance is mainly caused by structural reasons: 1) barriers between multiple layers in the contact region 2) Schottky barrier between metal and contact pad. These two barriers work as bottleneck of the system conductance. The extracted contact resistance matches with the experimental value. The approximation of contact resistance from quantum transport simulation can be very useful to guide better contact designs of the future technology nodes. ^ The theoretical modeling of these nano-scale devices demands a proper treatment of quantum effects such as the energy-level quantization caused by strong quantum confinement of electrons and band structure non-parabolicity. 2-D and 3-D quantum transport simulator that solves non-equilibrium Green\u27s functions (NEGF) transport and Poisson equations self-consistently within a real-space effective mass approximation. The sp3d5s* empirical tight-binding method is employed to include non-parabolicity to obtain more accurate effective masses in confined nano-structures. The accomplishment of this work would aid in designing, engineering and manufacturing nano-scale devices, as well as next-generation microchips and other electronics with nano-scale features

Numerical simulation of advanced CMOS and beyond CMOS devices

Co-supervisore: Marco PalaopenLo scaling dei dispositivi elettronici e l'introduzione di nuove opzioni tecnologiche per l'aumento delle prestazioni richiede un costante supporto dal punto di vista della simulazione numerica. Questa tesi si inquadra in tale ambito ed in particolare si prefigge lo scopo di sviluppare due tool software completi basati su tecniche avanzate al fine di predire le prestazioni di dipositivi nano-elettronici progettati per i futuri nodi tecnologiciDottorato di ricerca in Ingegneria industriale e dell'informazioneembargoed_20131103Conzatti, Francesc

Simulation of multigate SOI transistors with silicon, germanium and III-V channels

In this work by employing numerical three-dimensional simulations we study the electrical performance and short channel behavior of several multi-gate transistors based on advanced SOI technology. These include FinFETs, triple-gate and gate-all-around nanowire FETs with different channel material, namely Si, Ge, and III-V compound semiconductors, all most promising candidates for future nanoscale CMOS technologies. Also, a new type of transistor called “junctionless nanowire transistor” is presented and extensive simulations are carried out to study its electrical characteristics and compare with the conventional inversion- and accumulation-mode transistors. We study the influence of device properties such as different channel material and orientation, dimensions, and doping concentration as well as quantum effects on the performance of multi-gate SOI transistors. For the modeled n-channel nanowire devices we found that at very small cross sections the nanowires with silicon channel are more immune to short channel effects. Interestingly, the mobility of the channel material is not as significant in determining the device performance in ultrashort channels as other material properties such as the dielectric constant and the effective mass. Better electrostatic control is achieved in materials with smaller dielectric constant and smaller source-to-drain tunneling currents are observed in channels with higher transport effective mass. This explains our results on Si-based devices. In addition to using the commercial TCAD software (Silvaco and Synopsys TCAD), we have developed a three-dimensional Schrödinger-Poisson solver based on the non-equilibrium Green’s functions formalism and in the framework of effective mass approximation. This allows studying the influence of quantum effects on electrical performance of ultra-scaled devices. We have implemented different mode-space methodologies in our 3D quantum-mechanical simulator and moreover introduced a new method to deal with discontinuities in the device structures which is much faster than the coupled-mode-space approach