Green on-chip inductors in three-dimensional integrated circuits

This thesis focuses on the technique for the improvement of quality factor and inductance of the TSV inductors and then on the utilization of TSV inductors in various on-chip applications such as DC-DC converter and resonant clocking. Through-silicon-vias (TSVs) are the enabling technique for three-dimensional integrated circuits (3D ICs). However, their large area significantly reduces the benefits that can be obtained by 3D ICs. On the other hand, a major limiting factor for the implementation of many on-chip circuits such as DC-DC converters and resonant clocking is the large area overhead induced by spiral inductors. Several works have been proposed in the literature to make inductors out of idle TSVs. In this thesis, the technique to improve the quality factor and inductance is proposed and then discusses about two applications utilizing TSV inductors i.e., inductive DC-DC converters and LC resonant clocking. The TSV inductor performs inferior to spiral inductors due to its increases losses. Hence to improve the performance of the TSV inductor, the losses should be reduced. Inductive DC-DC converters become prominent for on-chip voltage conversion because of their high efficiency compared with other types of converters (e.g. linear and capacitive converters). On the other hand, to reduce on-chip power, LC resonant clocking has become an attractive option due to its same amplitude and phases compared to other resonant clocking methods such as standing wave and rotary wave. A major challenge for both applications is associated with the required inductor area. In this thesis, the effectiveness of such TSV inductors in addressing both challenges are demonstrated --Abstract, page iv

Manufacturing of three dimensional integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2007.Includes bibliographical references (p. 221-231).Along with scaling down in size, novel materials have been introduced into the semiconductor industry to enable continued improvements in performance and cost as predicted by Moore's law. It has become important now more than ever to include an environmental impact evaluation of future technologies, before they are introduced into manufacturing, in order to identify potentially environmentally harmful materials or processes and understand their implications, costs, and mitigation requirements. In this thesis, we introduce a methodology to compare alternative options on the environmental axis, along with the cost and performance axes, in order to create environmentally aware and benign technologies. This methodology also helps to identify potential performance and cost issues in novel technologies by taking a transparent and bottoms-up assessment approach. This methodology is applied to the evaluation of the MIT 3D IC technology in comparison to a standard CMOS 2D IC approach. Both options are compared on all three axes - performance, cost and environmental impact.(cont.) The "handle wafer" unit process in the existing 3D IC technology, which is a crucial process for back-to-face integration, is found to have a large environmental impact because of its use of thick metal sacrificial layers and high energy consumption. We explore three different handle wafer options, between-die channel, oxide release layer, and alternative low-temperature permanent bonding. The first two approaches use a chemical handle wafer release mechanism; while the third explores solid liquid inter-diffusion (SLID) bonding using copper-indium at 2000C. Preliminary results for copper-indium bonding indicate that a sub-micron thick multi-layer copper-indium stack, when bonded to a 300 nm thick copper film results in large voids in the bonding interface primarily due to rough as-deposited films. Finally, we conduct an overall assessment of these and other proposed handle wafer technologies. The overall assessment shows that but the oxide release layer approach appears promising; however, each process option has its strength and weaknesses, which need to be understood and pursued accordingly.by Ajay Somani.Ph.D

Design automation and analysis of three-dimensional integrated circuits

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Includes bibliographical references (p. 165-176).This dissertation concerns the design of circuits and systems for an emerging technology known as three-dimensional integration. By stacking individual components, dice, or whole wafers using a high-density electromechanical interconnect, three-dimensional integration can achieve scalability and performance exceeding that of conventional fabrication technologies. There are two main contributions of this thesis. The first is a computer-aided design flow for the digital components of a three-dimensional integrated circuit (3-D IC). This flow primarily consists of two software tools: PR3D, a placement and routing tool for custom 3-D ICs based on standard cells, and 3-D Magic, a tool for designing, editing, and testing physical layout characteristics of 3-D ICs. The second contribution of this thesis is a performance analysis of the digital components of 3-D ICs. We use the above tools to determine the extent to which 3-D integration can improve timing, energy, and thermal performance. In doing so, we verify the estimates of stochastic computational models for 3-D IC interconnects and find that the models predict the optimal 3-D wire length to within 20% accuracy. We expand upon this analysis by examining how 3-D technology factors affect the optimal wire length that can be obtained. Our ultimate analysis extends this work by directly considering timing and energy in 3-D ICs. In all cases we find that significant performance improvements are possible. In contrast, thermal performance is expected to worsen with the use of 3-D integration. We examine precisely how thermal behavior scales in 3-D integration and determine quantitatively how the temperature may be controlled during the circuit placement process. We also show how advanced packaging(cont.) technologies may be leveraged to maintain acceptable die temperatures in 3-D ICs. Finally, we explore two issues for the future of 3-D integration. We determine how technology scaling impacts the effect of 3-D integration on circuit performance. We also consider how to improve the performance of digital components in a mixed-signal 3-D integrated circuit. We conclude with a look towards future 3-D IC design tools.by Shamik Das.Ph.D

Thermal designs, models and optimization for three-dimensional integrated circuits

Three-dimensional integrated circuits (3D ICs), a novel packaging technology, are heavily studied to enable improved performance with denser packaging and reduced interconnects. Despite numerous advantages, thermal management is the biggest bottleneck to expanding the applications of this device stacking technology. In addition to implementing the thermal-aware designs of existing methodologies, it is necessary to implement new features to dissipate heat efficiently. This work presents two main aspects of thermal designs: on-chip level and package level. First, we propose a novel thermal-aware physical design on chip between devices. We aim to mitigate localized hotspots to ensure the functionality by adding thermal fin geometry to existing thermal through- silicon via (TTSV). We analyze design requirements of thermal fin for single TTSV as well as TTSV cluster designs with the goal of maximizing heat dissipation while minimizing the interference with routing and area consumption. An analytical model of the three-dimensional system and thermal resistance circuit is built for accurate and runtime-efficient thermal analysis. In terms of high-performance computing systems in 3D ICs, thermal bottle- necks are much more challenging with merely on-chip design solutions. Inter- tier liquid cooling microchannel layers have been introduced into 3D ICs as an integrated cooling mechanism to tackle the thermal degradation. Many existing research works optimize microchannel designs based on runtime-intensive numerical methods or inaccurate thermo-fluid models. Hence, we propose an accurate but compact closed-form model of tapered microchannel to capture the relationship between the channel geometry and heat transfer performance. To improve the accuracy, our correlations are based on the developing flow model and derived from numerical simulation data on a sub- set of multiple channel parameters. Our model achieves 57% less error in Nusselt number and 45 % less error in pressure drop for channels with inlet width 100-400 μm compared to a commonly used approximate model on fully developed flow. Next, we present the correlations for diverging channels as well as complete correlations that extend to any linearly tapering channel models, that include diverging shape, uniformly rectangular shape and converging shape. The complete models provide the flexibility to analyze and optimize any arbitrary geometry based on the piecewise linear channel wall assumption. Finally, we demonstrate the optimized channel designs using the derived correlations. Tapered channel models provided the flexibility to incorporate any arbitrary shapes and explore the advanced geometries during the optimization. The microchannel is divided into small segments in axial direction from inlet to outlet and piecewise optimized. The simulated annealing method is applied in our optimization, and channel width at one randomly chosen segment interface is altered to evaluate the design at each iteration. The objective is to minimize the overall thermal resistance while pressure drop is maintained less than a threshold value and channel widths have minimum and maximum boundaries. We compare the designs with the optimization based on fully developed flow models and verify the channel performance through numerical simulations. To guarantee optimality, accurate analysis is crucial. Our proposed models have significantly improved the accuracy by applying the appropriate flow assumption. However, many opportunities exist to increase the design flexibility and the accuracy. Fluid conditions, such as coolant material and varying volumetric flow rate, can also be part of the optimization parameters to expand the design scope. Moreover, physical phenomena, such as reduced friction on the channel walls or a vortex created on abrupt angle changes, can be considered to improve the accuracy in the closed-form models

Effects of stress and electromigration on microstructural evolution in microbumps of three-dimensional integrated circuits

Due to geometric scaling, the heterogeneous and anisotropic microstructures present in through-silicon vias and microbumps must be considered in the stress management of 3-D integrated circuits. In this paper, a phase field model is developed to investigate the effects of stress and electromigration on microstructural evolution in a Cu/Sn-microbump/Cu structure at 150 °C. External compressive stress is observed to accelerate the growth of Cu3Sn grains and cause the separation of continuous interfacial Cu 6 Sn 5 grains by β-Sn grains, whereas tensile stress promotes the growth of Cu 6 Sn 5 grains and the formation of a continuous Cu 6 Sn 5 layer. The roughness of the β-Sn-Cu 6 Sn 5 interface under compressive stress is greater than that under tensile stress. The morphological evolution of the β-Sn grains is also affected by stress. An external shear or compressive stress favors the growth of the β-Sn grains with their c-axis particular to the Y -direction. Furthermore, the interdiffusion flux driven by electromigration increases the roughness of the interfacial Cu 6 Sn 5 grains at the cathode. The strain caused by electromigration results in larger β-Sn grains, enabling faster interdiffusion along the current direction. The preferential growth of the β-Sn grains under stress or electromigration decreases the shear modulus of microbumps

Laser Crystallization of Silicon Thin Films for Three-Dimensional Integrated Circuits

The three-dimensional integration of microelectronics is a standard that has been actively pursued by numerous researchers in a variety of technical ways over the years. The primary aim of three-dimensional integration is to alleviate the well-known issues associated with device shrinking in conjunction with Moore's Law. In this thesis, we utilize laser-based and other melt-mediated crystallization techniques to create Si thin films that may be of sufficient microstructural quality for use in monolithic thin-film-based three-dimensional integrated circuits (3D-ICs). Beam-induced solidification of initially amorphous or polycrystalline Si films has been actively investigated over the years as an unconventional, yet often-effective, technical means to generate Si films with suitable microstructures for fabricating high-performance electronic devices. Two specific melt-mediated methods that are aimed at crystallizing Si thin films for 3D-ICs are presented. One is referred to as "advanced sequential lateral solidification (SLS)" while the other is referred to as "advanced mixed-phase solidification (MPS)" and we show that these approaches can provide a more 3D-IC-optimal microstructure than can be generated using previous deposition and/or crystallization-based techniques. Advanced SLS, as presented in this thesis, is a novel implementation of the previously-developed directional-SLS method, and is specifically aimed at addressing the microstructural non-uniformity issue that can be encountered in the directional solidification processing of continuous Si films. Films crystallized via the directional-SLS method, for instance, can contain physically distinct regions with varying densities of planar defects and/or crystallographic orientations. As a result, transistors fabricated within such films can potentially exhibit relatively poor device uniformity. To address this issue, we employ advanced SLS whereby Si films are prepatterned into closely-spaced, long, narrow stripes that are then crystallized via directional-SLS in the long-axis-direction of the stripe length. By doing so, one can create microstructurally distinct regions within each stripe, which are then placed within the active channel region of a device. It is shown that when the stripes are sufficiently narrow (less than 2 µm), a bi-crystal microstructure is observed. This is explained based on the change in the interface morphology as a consequence of enhanced heat flow at the edges of the stripe. It is suggested that this bi-crystal formation is beneficial to the approach, as it increases the effective number of stripes within the active channel region. One issue of fundamental and technological significance that is nearly always encountered in laser crystallization is the formation of structural defects, in general, and in particular, twins. Due to the importance of reducing the density of these defects in order to increase the performance of transistors, this thesis investigates the formation mechanism of twins in rapidly laterally solidified Si thin films. These defects have been characterized and examined in the past, but a physically consistent explanation has not yet been provided. To address this situation, we have carried out experiments using a particular version of SLS, namely dot-SLS. This specific technique is chosen because we identify that it is endowed with a fortuitous combination of experimental factors that enable the systematic examination of twinning in laterally grown Si thin films. Based on extensive microstructural analysis of dot-SLS-crystallized regions, we propose that it is the energetics associated with forming a new atomic layer (during growth) in either a twinned or non-twinned configuration heterogeneously at the oxide/film interface that dictate the formation (or absence) of twins. The second method presented in this thesis is that of advanced MPS. The basic MPS approach was originally conceived as a way to generate Si films for solar cells as it is capable of producing large, intragrain-defect-free regions that are predominantly (100) surface-textured. However, the location of the grain boundaries of these equiaxed grains is essentially random, and hence, transistors placed within the interior of the grains would exhibit differing performance compared to those that are place across the grain boundaries. To address this, advanced MPS is introduced and demonstrated as a means to manipulate solidification by seeding from {100} surface-oriented regions and to induce limited directional growth. This is accomplished using a continuous-wave laser with a Gaussian-shaped beam profile wherein a central, completely molten region is surrounded by a ``mixed-phase-region'' undergoing MPS. The technique creates quasi-directional material that consists of large, elongated, parallel, {100} surface-oriented grains. This material is an improvement over previously generated directionally solidified materials, and can allow one to build devices without high angle grain boundaries that are within, and oriented perpendicular to, the active channel. The resulting microstructure is explained in terms of the non-uniform energy density distribution generated by the Gaussian-shaped laser beam, and the corresponding shape and growth of the solid/liquid interface. Based on the observations and considerations from these results, we propose and demonstrate a related scheme whereby a flash-lamp annealing system is utilized in order to induce the advanced MPS condition. This method can potentially time-efficiently crystallize, and create in the process, well-defined regions that are microstructurally suitable for the fabrication of 3D-ICs

X‐ray microscopy and automatic detection of defects in through silicon vias in three‐dimensional integrated circuits

Through silicon vias (TSVs) are a key enabling technology for interconnection and realization of complex three-dimensional integrated circuit (3D-IC) components. In order to perform failure analysis without the need of destructive sample preparation, x-ray microscopy (XRM) is a rising method of analyzing the internal structure of samples. However, there is still a lack of evaluated scan recipes or best practices regarding XRM parameter settings for the study of TSVs in the current state of literature. There is also an increased interest in automated machine learning and deep learning approaches for qualitative and quantitative inspection processes in recent years. Especially deep learning based object detection is a well-known methodology for fast detection and classification capable of working with large volumetric XRM datasets. Therefore, a combined XRM and deep learning object detection workflow for automatic micrometer accurate defect location on liner-TSVs was developed throughout this work. Two measurement setups including detailed information about the used parameters for either full IC device scan or detailed TSV scan were introduced. Both are able to depict delamination defects and finer structures in TSVs with either a low or high resolution. The combination of a 0.4 objective with a beam voltage of 40 kV proved to be a good combination for achieving optimal imaging contrast for the full-device scan. However, detailed TSV scans have demonstrated that the use of a 20 objective along with a beam voltage of 140 kV significantly improves image quality. A database with 30,000 objects was created for automated data analysis, so that a well-established object recognition method for automated defect analysis could be integrated into the process analysis. This RetinaNet-based object detection method achieves a very strong average precision of 0.94. It supports the detection of erroneous TSVs in both top view and side view, so that defects can be detected at different depths. Consequently, the proposed workflow can be used for failure analysis, quality control or process optimization in R&D environments