Fog computing, applications , security and challenges, review

The internet of things originates a world where on daily basis objects can join the internet and interchange information and in addition process, store, gather them from the nearby environment, and effectively mediate on it. A remarkable number of services might be imagined by abusing the internet of things. Fog computing which is otherwise called edge computing was introduced in 2012 as a considered is a prioritized choice for the internet of things applications. As fog computing extend services of cloud near to the edge of the network and make possible computations, communications, and storage services in proximity to the end user. Fog computing cannot only provide low latency, location awareness but also enhance real-time applications, quality of services, mobility, security and privacy in the internet of things applications scenarios. In this paper, we will summarize and overview fog computing model architecture, characteristic, similar paradigm and various applications in real-time scenarios such as smart grid, traffic control system and augmented reality. Finally, security challenges are presented

3D MPSoC Design Using 2D EDA tools: Analysis of Parameters

International audienceDesign space exploration of 3D MPSoC architecture is reported in this paper analyzing the impact of 2D EDA tools to the 3D architecture performance. In particular, we study how 3D performance is varied when changing the EDA tools options intending to highlight design issues of 3D design. Results show that 3D timing performance is affected greatly compared with power consumption and total wirelength

Universal Three Dimensional Optical Logic

Modern integrated circuits are essentially two-dimensional (2D). Partial three-dimensional (3D) integration and 3D-transistor-level integrated circuits have long been anticipated as routes to improve the performance, cost and size of electronic computing systems. Even as electronics approach fundamental limits however, stubborn challenges in 3D circuits, and innovations in planar technology have delayed the dimensional transition. Optical computing offers potential for new computing approaches, substantially greater performance and would complement technologies in optical interconnects and data storage. Nevertheless, despite some progress, few proposed optical transistors possess essential features required for integration into real computing systems. Here we demonstrate a logic gate based on universal features of nonlinear wave propagation: spatiotemporal instability and collapse. It meets the scaling criteria and enables a 3D, reconfigurable, globally-hyperconnected architecture that may achieve an exponential speed up over conventional platforms. It provides an attractive building block for future optical computers, where its universality should facilitate flexible implementations.Comment: manuscript (5 pages, 3 figures) with supplementary information (6 pages, 5 figures

Radiation safety based on the sky shine effect in reactor

In the reactor operation, neutrons and gamma rays are the most dominant radiation. As protection, lead and concrete shields are built around the reactor. However, the radiation can penetrate the water shielding inside the reactor pool. This incident leads to the occurrence of sky shine where a physical phenomenon of nuclear radiation sources was transmitted panoramic that extends to the environment. The effect of this phenomenon is caused by the fallout radiation into the surrounding area which causes the radiation dose to increase. High doses of exposure cause a person to have stochastic effects or deterministic effects. Therefore, this study was conducted to measure the radiation dose from sky shine effect that scattered around the reactor at different distances and different height above the reactor platform. In this paper, the analysis of the radiation dose of sky shine effect was measured using the experimental metho

Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them

Thermal management of the through silicon vias in 3-D integrated circuits

The through silicon via technology is a promising and preferred way to realize the reliable interconnection for 3-D integrated circuit integration. However, its size and the property of the filled-materials are two factors affecting the thermal behavior of the integrated circuits. In this paper, we design 3-D integrated circuits with different through silicon via models and analyze the effect of different material-filled through silicon vias, aspect ratio and thermal conductivity of the dielectric on the steady-state temperature profiles. The results presented in this paper are expected to aid in the development of thermal design guidelines for through silicon vias in 3-D integrated circuits

Color-tunable and Phosphor-free White-light Multi-layered Light-emitting Diodes

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Seamless monolithic three-dimensional integration of single-crystalline films by growth

The demand for the three-dimensional (3D) integration of electronic components is on a steady rise. The through-silicon-via (TSV) technique emerges as the only viable method for integrating single-crystalline device components in a 3D format, despite encountering significant processing challenges. While monolithic 3D (M3D) integration schemes show promise, the seamless connection of single-crystalline semiconductors without intervening wafers has yet to be demonstrated. This challenge arises from the inherent difficulty of growing single crystals on amorphous or polycrystalline surfaces post the back-end-of-the-line process at low temperatures to preserve the underlying circuitry. Consequently, a practical growth-based solution for M3D of single crystals remains elusive. Here, we present a method for growing single-crystalline channel materials, specifically composed of transition metal dichalcogenides, on amorphous and polycrystalline surfaces at temperatures lower than 400 {\deg}C. Building on this developed technique, we demonstrate the seamless monolithic integration of vertical single-crystalline logic transistor arrays. This accomplishment leads to the development of unprecedented vertical CMOS arrays, thereby constructing vertical inverters. Ultimately, this achievement sets the stage to pave the way for M3D integration of various electronic and optoelectronic hardware in the form of single crystals

Posicionamento de Circuitos 3D Considerando o Planejamento de 3D-Vias

Este trabalho explora métodos para realizar o posicionamento de um tipo particular de circuitos VLSI conhecido como circuito 3D (três dimensões).. Diferente de trabalhos anteriores, este artigo aborda o problema de posicionamento 3D considerando as conexões verticais (chamadas 3D-Vias) e as limitações impostas pelas mesmas. Foi realizado um ?uxo completo de posicionamento, iniciando pelo tratamento de pinos de entrada e saída (E/S) e seguido com posicionamento global, posicionamento detalhado e posicionamento das 3D-Vias. A primeira etapa busca a distribuição os pinos de E/S de maneira equilibrada objetivando auxiliar o posicionamento para obter uma quantidade reduzida de 3D-Vias. O mecanismo de posicionamento global baseado no algorítmo de Quadratic Placement considera informações fornecidos pela tecnologia de fabricação e requisito de espaçamento de 3D-Vias para reduzir o comprimento das conexões e equilibrar a distribuição das células em 3D. Conexões críticas podem ser tratadas através da inserção de redes arti?ciais que auxiliam a evitar que 3D-Vias sejam usadas em sua implementação. Finalmente, as 3D-Vias são posicionadas por um algorítmo rápido baseado na legalização Tetris. O framework completo reforça os potenciais benefícios dos circuitos 3D para reduzir o comprimento das co- nexões e apresenta algorítmos e?cientes projetados para circuitos 3D que podem ser incorporados em novas ferramentas de CAD

Test Cost Analysis for 3D Die-to-Wafer Stacking

The industry is preparing itself for three-dimensional stacked ICs (3D-SICs); a technology that promises hetero-geneous integration with higher performance and lower power dissipation at a smaller footprint. Several 3D stacking approaches are under development. From a yield point of view, Die-to-Wafer (D2W) stacking seems the most favorable approach, due to the ability of Known Good Die stacking. Minimizing the test cost for such a stacking approach is a challenging task. Every manufactured chip has to be tested, and any tiny test saving per 3D-SIC impacts the overall cost, especially in high-volume produc-tion. This paper establishes a cost model for D2W SICs and investigates the impact of the test cost for different test flows. It first introduces a framework covering different test flows for 3D D2W ICs. Subsequently, it proposes a test cost model to estimate the impact of the test flow on the overall 3D-SIC cost. Our simulation results show that (a) test flows with pre-bond testing significantly reduce the overall cost, (b) a cheaper test flow does not necessary result in lower overall cost, (c) test flows with intermediate tests (performed during the stacking process) pay off, (d) the most cost-effective test flow consists of pre-bond tests and strongly depends on the stack yield; hence, adapting the test according the stack yield is the best approach to use