Accelerated Aging System for Prognostics of Power Semiconductor Devices

Prognostics is an engineering discipline that focuses on estimation of the health state of a component and the prediction of its remaining useful life (RUL) before failure. Health state estimation is based on actual conditions and it is fundamental for the prediction of RUL under anticipated future usage. Failure of electronic devices is of great concern as future aircraft will see an increase of electronics to drive and control safety-critical equipment throughout the aircraft. Therefore, development of prognostics solutions for electronics is of key importance. This paper presents an accelerated aging system for gate-controlled power transistors. This system allows for the understanding of the effects of failure mechanisms, and the identification of leading indicators of failure which are essential in the development of physics-based degradation models and RUL prediction. In particular, this system isolates electrical overstress from thermal overstress. Also, this system allows for a precise control of internal temperatures, enabling the exploration of intrinsic failure mechanisms not related to the device packaging. By controlling the temperature within safe operation levels of the device, accelerated aging is induced by electrical overstress only, avoiding the generation of thermal cycles. The temperature is controlled by active thermal-electric units. Several electrical and thermal signals are measured in-situ and recorded for further analysis in the identification of leading indicators of failures. This system, therefore, provides a unique capability in the exploration of different failure mechanisms and the identification of precursors of failure that can be used to provide a health management solution for electronic devices

System and Component Failure from Electrical Overstress and Electrostatic Discharge

Electrical overstress (EOS) and electrostatic discharge (ESD) have been an issue in devices, circuit and systems for electronics for many decades, as early as the 1970s, and continued to be an issue to today. In this chapter, the issue of EOS and ESD will be discussed. The sources of both EOS and ESD failure history will be discussed. EOS and ESD physical models, failure mechanisms, testing methods and solutions will be shown. The chapter will close with discussion on how to provide both EOS and ESD robust devices, circuits, and systems, design practices, and procedures, as well as EOS and ESD factory control programs. EOS sources also occur from design characteristics of devices, circuits, and systems

Modeling of the impact of electrical stressors on the degradation process of Power MOSFETs

This research focused on building a model based on collection of experimental data acquired with high electrical stressors at the gate of the power MOSFET under an isothermal condition to analyze certain deviations of intrinsic properties leading to degradation. The primary indicators were threshold shift, deviation in switching characteristics, and significant expansion of the Miller Plateau due to accelerated stressing of the device from the pristine condition. The intrinsic mechanism associated with the threshold shift and changes in the parasitic capacitances were observed and analyzed with mathematical precision and device parameter simulation. It was seen that, in addition to altered switching behavior and other changes, the threshold voltage shifted by 172%, the width of the Miller Plateau increased by 525%, and capacitances decreased by 24~43% at applied stress of 45V to 54V in addition to altered switching behavior and other changes. This behavior showed deviation; however, degradation did not occur. The root cause of the modified behavior of a stressed device was also analyzed. The 2D device-processing software Sentaurus correlated the experimental observations

Prognostics for Electronics Components of Avionics Systems

Electronics components have and increasingly critical role in avionics systems and for the development of future aircraft systems. Prognostics of such components is becoming a very important research filed as a result of the need to provide aircraft systems with system level health management. This paper reports on a prognostics application for electronics components of avionics systems, in particular, its application to the Isolated Gate Bipolar Transistor (IGBT). The remaining useful life prediction for the IGBT is based on the particle filter framework, leveraging data from an accelerated aging tests on IGBTs. The accelerated aging test provided thermal-electrical overstress by applying thermal cycling to the device. In-situ state monitoring, including measurements of the steady-state voltages and currents, electrical transients, and thermal transients are recorded and used as potential precursors of failure

Towards Prognostics for Electronics Components

Electronics components have an increasingly critical role in avionics systems and in the development of future aircraft systems. Prognostics of such components is becoming a very important research field as a result of the need to provide aircraft systems with system level health management information. This paper focuses on a prognostics application for electronics components within avionics systems, and in particular its application to an Isolated Gate Bipolar Transistor (IGBT). This application utilizes the remaining useful life prediction, accomplished by employing the particle filter framework, leveraging data from accelerated aging tests on IGBTs. These tests induced thermal-electrical overstresses by applying thermal cycling to the IGBT devices. In-situ state monitoring, including measurements of steady-state voltages and currents, electrical transients, and thermal transients are recorded and used as potential precursors of failure

Analysis of design strategies for RF ESD problems in CMOS circuits

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip

Master of Science

dissertationPower converters are frequently exposed to electrical stresses such as over voltage, over current and switching impulses during their regular operations. These stresses may not result in immediate failure of a power converter. However, over longer periods they cause gradual degradation of critical components inside the converter, which ultimately leads to a complete failure of the converter. Failure of a power converter might disrupt the operation of the entire system, occasionally causing catastrophic outcomes. Estimating a converter's state of health and predicting the remaining life involves extensive research in semiconductor device physics and circuit theory, and is both important and challenging. There is always a dire need to determine the level of aging in power converters so that an approximate time to failure could be predicted. A reflectometry technique was applied to power converters to identify failure and aging associated to critical components inside a power converter. In addition, mechanisms for gradual shift in measurable electrical parameters of power converter components over long durations have been studied under the scope of the project. While there exist several other techniques for predicting reliability and aging of power converters, they are limited to characterizing isolated components only. Whereas using the proposed technique, estimating the component degradation in energized circuits is possible. Spread spectrum time domain reflectometry (SSTDR) has been commercially used for detecting aircraft wiring faults during the last decade, however, it was never applied to components in a power converter. During the preliminary stage of this project SSTDR was applied to a DC-DC converter circuit, and several key parameters such as MOSFETs ON resistance was extracted to characterize MOSFET aging. Later on, this technique was applied to different other components in an H-bridge AC-AC converter for failure rate estimation and reliability analysis. The MTTF (mean time to failure) was calculated based on the SSTDR generated data. The conducted research has initiated other SSTDR based prognostics and state of health measurement methods applicable to PV panels, electric machines and batteries

Prognostics of Power Mosfets Under Thermal Stress Accelerated Aging Using Data-Driven and Model-Based Methodologies

An approach for predicting remaining useful life of power MOSFETs (metal oxide field effect transistor) devices has been developed. Power MOSFETs are semiconductor switching devices that are instrumental in electronics equipment such as those used in operation and control of modern aircraft and spacecraft. The MOSFETs examined here were aged under thermal overstress in a controlled experiment and continuous performance degradation data were collected from the accelerated aging experiment. Dieattach degradation was determined to be the primary failure mode. The collected run-to-failure data were analyzed and it was revealed that ON-state resistance increased as die-attach degraded under high thermal stresses. Results from finite element simulation analysis support the observations from the experimental data. Data-driven and model based prognostics algorithms were investigated where ON-state resistance was used as the primary precursor of failure feature. A Gaussian process regression algorithm was explored as an example for a data-driven technique and an extended Kalman filter and a particle filter were used as examples for model-based techniques. Both methods were able to provide valid results. Prognostic performance metrics were employed to evaluate and compare the algorithms

Towards Prognostics of Power MOSFETs: Accelerated Aging and Precursors of Failure

This paper presents research results dealing with power MOSFETs (metal oxide semiconductor field effect transistor) within the prognostics and health management of electronics. Experimental results are presented for the identification of the on-resistance as a precursor to failure of devices with die-attach degradation as a failure mechanism. Devices are aged under power cycling in order to trigger die-attach damage. In situ measurements of key electrical and thermal parameters are collected throughout the aging process and further used for analysis and computation of the on-resistance parameter. Experimental results show that the devices experience die-attach damage and that the on-resistance captures the degradation process in such a way that it could be used for the development of prognostics algorithms (data-driven or physics-based)

Reliability Assessment of IGBT through Modelling and Experimental Testing

Lifetime of power electronic devices, in particular those used for wind turbines, is short due to the generation of thermal stresses in their switching device e.g., IGBT particularly in the case of high switching frequency. This causes premature failure of the device leading to an unreliable performance in operation. Hence, appropriate thermal assessment and implementation of associated mitigation procedure are required to put in place in order to improve the reliability of the switching device. This paper presents two case studies to demonstrate the reliability assessment of IGBT. First, a new driving strategy for operating IGBT based power inverter module is proposed to mitigate wire-bond thermal stresses. The thermal stress is characterised using finite element modelling and validated by inverter operated under different wind speeds. High-speed thermal imaging camera and dSPACE system are used for real time measurements. Reliability of switching devices is determined based on thermoelectric (electrical and/or mechanical) stresses during operations and lifetime estimation. Second, machine learning based data-driven prognostic models are developed for predicting degradation behaviour of IGBT and determining remaining useful life using degradation raw data collected from accelerated aging tests under thermal overstress condition. The durations of various phases with increasing collector-emitter voltage are determined over the device lifetime. A data set of phase durations from several IGBTs is trained to develop Neural Network (NN) and Adaptive Neuro Fuzzy Inference System (ANFIS) models, which is used to predict remaining useful life (RUL) of IGBT. Results obtained from the presented case studies would pave the path for improving the reliability of IGBTs