Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Theory, Modelling and Implementation of Graphene Field-Effect Transistor

PhDTwo-dimensional materials with atomic thickness have attracted a lot of attention from researchers worldwide due to their excellent electronic and optical properties. As the silicon technology is approaching its limit, graphene with ultrahigh carrier mobility and ultralow resistivity shows the potential as channel material for novel high speed transistor beyond silicon. This thesis summarises my Ph.D. work including the theory and modelling of graphene field-effect transistors (GFETs) as well as their potential RF applications. The introduction and review of existing graphene transistors are presented. Multiscale modelling approaches for graphene devices are also introduced. A novel analytical GFET model based on the drift-diffusion transport theory is then developed for RF/microwave circuit analysis. Since the electrons and holes have different mobility variations against the channel potential in graphene, the ambipolar GFET cannot be modelled with constant carrier mobility. A new carrier mobility function, which enables the accurate modelling of the ambipolar property of GFET, is hence developed for this purpose. The new model takes into account the carrier mobility variation against the bias voltage as well as the mobility difference between electrons and holes. It is proved to be more accurate for the DC current calculation. The model has been written in Verilog-A language and can be import into commercial software such as Keysight ADS for circuit simulation. In addition, based on the proposed model two GFET non-Foster circuits (NFCs) are conducted. As a negative impedance element, NFCs find their applications in impedance matching of electrically small antennas and bandwidth improvement of metasurfaces. One of the NFCs studied in this thesis is based on the Linvill's technique in which a pair of identical GFETs is used while the other circuit utilises the negative resistance of a single GFET. The stability analysis of NFCs is also presented. Finally, a high impedance surface loaded with proposed NFCs is also studied, demonstrating significant bandwidth enhancement.Engineering and Physical Sciences Research Council (EPSRC) Grant on `Graphene Flexible Electronics and Optoelectronics' (EP/K01711X/1), the EU Graphene Flagship (FP7-ICT-604391) and Graphene Core 1 (H2020 696656

Development of advanced technologies for the fabrication of III-V high electron mobility transistors

Over the past 5 years there has been an increase in the number of applications that require devices that operate in the millimetre range (30-300GHz). This demand has driven research into " devices that will operate at frequencies above 100GHz. This performance has been achieved using two main technologies, the Heterojunction Bipolar Transistor (HBT) and the High Electron Mobility Transistor (HEMT). At present it is a HEMT device that holds the record for the highest operating frequency of any transistor. It is this technology that this project concentrates on. In order to fabricate devices that operate at these frequencies two methods are commonly employed. The first is to vary the material of the device, in particular, increasing the indium content of the channel. The second method is to reduce the physical dimensions of the transistors, including reducing the gate length of the device therefore reducing transit time and gate capacitance. Reducing the separation of the source-drain ohmic contacts or employing a self-aligned ohmic strategy reduces the associated parasitic resistances. This project will concentrate on the scaling of the gate length in addition to the reduction of parasitic resistances with the use of self-aligned ohmic contacts.This work includes the realisation of the first self-aligned 120nm T -Gate. GaAs pHEMT fabricated at the University of Glasgow. These devices required the development of two key technologies, the non-annealed ohmic contact and the succinic acid based selective wet etch. The self-aligned devices showed good RF performance with a ft of 150 GHz and a fmax of 180 GHz which compares favourable with results o~ 120nm GaAs pHEMTs previously fabricated at Glasgow. The investigation of gate length scaling to device performance included the development of two lithographic process capable of producing HEMT with a gate length of 50nm and 30nm respectively in addition to a method ~f sample preparation that allows these devices to be analysed using TEM techniques. This work has lead to the realisation of SOnm T -gate metamorphic HEMTs using a PMMAIcopolymer resist stack, these devices displayed an excellent yield, with over 95% of devices working. The uniformity of the gate process was also high with a threshold voltage of - 0.44SV with a standard deviation of O.OOSV. The devices demonstrated an .it of 330GHz and a fmax of 260GHz making these devices some of the fastest transistors that have ever been fabricated on a GaAs substrate. The second lithography process was developed to realise T -gates with a gate length of less than SOnm. This processed used a two stage "bi-lithography" process to minimise the effect of forward s7attering through the resist. The gate footprint was transferred into a Si02 gate by a dry etch process. This lithography process was integrated into a full process flow for lattice matched InP HEMTs Using this process, HEMTs were fabricated with a T-gate of 2Snm. This is the smallest T -gate device that has been fabricated at the University of Glasgow and is comparable with the smallest HEMT devices in the world

MC 2019 Berlin Microscopy Conference - Abstracts

Das Dokument enthält die Kurzfassungen der Beiträge aller Teilnehmer an der Mikroskopiekonferenz "MC 2019", die vom 01. bis 05.09.2019, in Berlin stattfand

Variability and reliability analysis of carbon nanotube technology in the presence of manufacturing imperfections

In 1925, Lilienfeld patented the basic principle of field effect transistor (FET). Thirty-four years later, Kahng and Atalla invented the MOSFET. Since that time, it has become the most widely used type of transistor in Integrated Circuits (ICs) and then the most important device in the electronics industry. Progress in the field for at least the last 40 years has followed an exponential behavior in accordance with Moore¿s Law. That is, in order to achieve higher densities and performance at lower power consumption, MOS devices have been scaled down. But this aggressive scaling down of the physical dimensions of MOSFETs has required the introduction of a wide variety of innovative factors to ensure that they could still be properly manufactured. Transistors have expe- rienced an amazing journey in the last 10 years starting with strained channel CMOS transistors at 90nm, carrying on the introduction of the high-k/metal-gate silicon CMOS transistors at 45nm until the use of the multiple-gate transistor architectures at 22nm and at recently achieved 14nm technology node. But, what technology will be able to produce sub-10nm transistors? Different novel materials and devices are being investigated. As an extension and enhancement to current MOSFETs some promising devices are n-type III-V and p-type Germanium FETs, Nanowire and Tunnel FETs, Graphene FETs and Carbon Nanotube FETs. Also, non-conventional FETs and other charge-based information carrier devices and alternative information processing devices are being studied. This thesis is focused on carbon nanotube technology as a possible option for sub-10nm transistors. In recent years, carbon nanotubes (CNTs) have been attracting considerable attention in the field of nanotechnology. They are considered to be a promising substitute for silicon channel because of their small size, unusual geometry (1D structure), and extraordinary electronic properties, including excellent carrier mobility and quasi-ballistic transport. In the same way, carbon nanotube field-effect transistors (CNFETs) could be potential substitutes for MOSFETs. Ideal CNFETs (meaning all CNTs in the transistor behave as semiconductors, have the same diameter and doping level, and are aligned and well-positioned) are predicted to be 5x faster than silicon CMOS, while consuming the same power. However, nowadays CNFETs are also affected by manufacturing variability, and several significant challenges must be overcome before these benefits can be achieved. Certain CNFET manufacturing imperfections, such as CNT diameter and doping variations, mispositioned and misaligned CNTs, high metal-CNT contact resistance, the presence of metallic CNTs (m-CNTs), and CNT density variations, can affect CNFET performance and reliability and must be addressed. The main objective of this thesis is to analyze the impact of the current CNFET manufacturing challenges on multi-channel CNFET performance from the point of view of variability and reliability and at different levels, device and circuit level. Assuming that CNFETs are not ideal or non-homogeneous because of today CNFET manufacturing imperfections, we propose a methodology of analysis that based on a CNFET ideal compact model is able to simulate heterogeneous or non-ideal CNFETs; that is, transistors with different number of tubes that have different diameters, are not uniformly spaced, have different source/drain doping levels, and, most importantly, are made up not only of semiconducting CNTs but also metallic ones. This method will allow us to analyze how CNT-specific variations affect CNFET device characteristics and parameters and CNFET digital circuit performance. Furthermore, we also derive a CNFET failure model and propose an alternative technique based on fault-tolerant architectures to deal with the presence of m-CNTs, one of the main causes of failure in CNFET circuits

Dilute-Anion III-Nitride Semiconductor Materials and Nanostructures

In this dissertation, the work focuses on the development of the dilute-anion III-Nitride based semiconductor for device applications in visible and deep ultraviolet (UV) spectral regime. First-Principle Density-Functional Theory calculations are employed for the investigation of optoelectronic properties of the dilute-anion III-Nitride semiconductors, which includes the understanding of alloy band structures and related band parameters. Among the dilute-anion III-Nitride semiconductor material class, dilute-As GaNAs, dilute-P GaNP and dilute-As AlNAs are extensively studied in this work. The findings show that the incorporation of anion-content in the GaN or AlN alloy will result in significant changes in the electronic properties, leading to unique features as compared to the conventional III-Nitride alloys such as InGaN and AlGaN alloys. Specifically, the investigation in the electronic properties of dilute-As GaNAs and dilute-P GaNP alloys result in suppression of interband Auger recombination process – a known efficiency-limiting issue in the InGaN quantum well (QW) light emitting diode devices., Further analysis are performed to design novel active region nanostructure of InGaN / dilute-As GaNAs interface QW for visible light emission. The analysis tindicate significantly enhanced spontaneous recombination rate and optical gain across the visible spectral regime from blue to red by using InGaN / dilute-As GaNAs interface QW, as compared to conventional InGaN QW. In the case of dilute-As AlNAs semiconductor, the analysis shows that the incorporation of minute amount of As-content in the AlN alloy will result in the switching of crystal field field split-off band with the heavy hole / light hole band, potentially solving the valence band crossover issue persisting in the AlGaN deep ultraviolet light emitting devices.In addition, extensive studies have been focused in the development of Auger recombination model taking into account the interface roughness in the QW, and analytical solutions for direct Auger recombination processes including interband Auger process for semiconductors. Specifically, the developed Auger model with interface roughness are important to provide intuitive insight of the role of Auger recombination process in the semiconductor devices employing nanostructures

1995 BRAC Commission

Naval Research Lab, Washington Site: Data Call. Tabular data, memos, documents. Box 178, L-110