Carrier Mobility in Field-Effect Transistors

Authors investigate the carrier mobility in field-effect transistors mainly when fabricated on Si(110) wafers. They showed that the methods developed to extract the conduction parameters cannot be implemented for Si(110) p-MOSFETs. Authors then developed a more accurate mobility model able to simulate not only the drivability but also the transconductance for these same devices. The study of the relation between the mobility, channel direction and wafer orientation revealed that the channel direction had a significant impact on the mobility for transistors fabricated on Si(110) wafers, the highest electron and hole mobilites being obtained for a channel along the and directions, respectively. No relations were found for Si(100) wafers. The study of the dependence of the scattering mechanism limiting the mobility in Si(110) n-MOSFETs showed that the Coulomb and surface roughness scattering mechanisms were responsible for the degradation of the mobility when compared to the one on Si(100) wafers. Finally, the measurement of the mobility in an accumulation-mode MOSFETs is not straightforward since a bulk contribution, owing to the SOI layer, is adding to channel current. A methodology has been successfully implemented that led to the experimental verification of the universal behaviour of the mobility in an accumulation layer

Development of a fully-depleted thin-body FinFET process

The goal of this work is to develop the processes needed for the demonstration of a fully-depleted (FD) thin-body fin field effect transistor (FinFET). Recognized by the 2003 International Technology Roadmap for Semiconductors as an emerging non-classical CMOS technology, FinFETs exhibit high drive current, reduced short-channel effects, an extreme scalability to deep submicron regimes. The approach used in this study will build on previous FinFET research, along with new concepts and technologies. The critical aspects of this research are: (1) thin body creation using spacer etchmasks and oxidation/etchback schemes, (2) use of an oxynitride gate dielectric, (3) silicon crystal orientation effect evaluation, and (4) creation of fully-depleted FinFET devices of submicron gate length on Silicon-on-Insulator (SOI) substrates. The developed process yielded functional FinFETs of both thin body and wide body variety. Electrical tests were employed to describe device behaviour, including their subthreshold characteristics, standard operation, effects of gate misalignment on device performance, and impact of crystal orientation on device drive current. The process is shown to have potential for deep submicron regimes of fin width and gate length, and provides a good foundation for further research of FinFETs and similar technologies at RIT

Investigation of the electrical properties of Si₁-×Ge× channel pMOSFETs with high-κ dielectrics

It is now apparent that the continued performance enhancements of silicon metal-oxide-semiconductor field effect transistors (MOSFETs) can no longer be met by scaling alone. High-mobility channel materials such as strained Si1-xGex and Ge are now being seriously considered to maintain the performance requirements specified by the semiconductor industry. In addition, alternative gate dielectric, or high-κ dielectrics, will also be required to meet gate leakage requirements. This work investigates the properties of using strained Si1-xGex or Ge as alternative channel materials for pMOSFETs incorporating hafnium oxide (HfO2) high-κ gate dielectric. Whilst the SiGe pMOSFETs (x = 0.25) exhibited an enhancement in hole mobility (300 K) over comparable silicon control pMOSFETs with sputtered HfO2 dielectric, high Coulomb scattering and surface roughness scattering relating to the dielectric deposition process meant that the effective hole mobilities were degraded with respect to the silicon universal curve. Germanium channel pMOSFETs with halo-doping and HfO2 gate dielectric deposited by atomic layer deposition showed high hole mobilities of 230 cm2V-1s-1 and 480 cm2V-1s-1 at room temperature and 77 K, respectively. Analysis of the off-state current for the Ge pMOSFETs over a range of temperatures indicated that band-to-band tunnelling, gate-induced drain leakage and other defect-assisted leakage mechanisms could all be important. Hole carrier velocity and impact ionisation were also studied in two batches of buried channel SiGe pMOSFET with x = 0.15 and x = 0.36, respectively. SiGe channel pMOSFETs were found to exhibit reduced impact ionisation compared to silicon control devices, which has been attributed to a strain-induced reduction of the density of states in the SiGe conduction and valence bands. Analysis of the hole carrier velocity indicated that pseudomorphic SiGe offered no performance enhancements over Si below 100 nm, possibly due to higher ion implantation damage and strain relaxation of the strained SiGe channel. The results indicate that velocity overshoot effects might not provide the performance improvements at short channel lengths that was previously hoped for

Characterisation of silicon carbide CMOS devices for high temperature applications

PhD ThesisIn recent years it has become increasingly apparent that there is a large demand for resilient electronics that can operate within environments that standard silicon electronics cease to function such as high power and high voltage applications, high temperatures, corrosive atmospheres and environments exposed to radiation. This has become even more essential due to increased demands for sustainable energy production and the reduction in carbon emissions worldwide, which has put a large burden on a wide range of industrial sectors who now have a significant demand for electronics to meet these needs including; military, space, aerospace, automotive, energy and nuclear. In extreme environments, where ambient temperatures may well exceed the physical limit of silicon-based technologies, SiC based technology offers a lower cost and a smaller footprint solution for operation in such environments due to its advantageous electrical properties such as a high breakdown electric field, high thermal conductivity and large saturation velocity. High quality material on large area wafers (150 mm) is now commercially available, allowing the fabrication of reliable high temperature, high frequency and high current power electronic devices, improving the already optimised silicon based structures. An important advantage of SiC is that it is the only wide band gap compound semiconductor that can be thermally oxidised to grow insulating, high quality SiO2 layers, which makes it an ideal candidate to replace silicon technologies for metal-oxide-semiconductor applications, which is the main focus of this research. Although the technology has made a number of major steps forward over recent years and the commercial manufacturing process has advanced significantly, there still remains a number of issues that need to be overcome in order to fully realise the potential of the material for electronic applications. This thesis describes the characterisation of 4H-SiC CMOS structures that were designed for high temperature applications and fabricated with varying gate dielectric treatments and process steps. The influence of process techniques on the characteristics of metal-oxide-semiconductor (MOS) devices has been investigated by means of electrical characterisation and the results have been compared to theoretical models. The C-V and I-V characteristics of both MOS capacitor and MOSFET structures with varying gate dielectrics on both n-type and p-type 4H-SiC have been analysed to explore the benefits of the varying process techniques that have been employed in the design of the devices. The results show that the field effect mobility characteristic of 4H-SiC MOSFETs are dominated at low perpendicular electric fields by Coulomb scattering and at high electric fields by low surface roughness mobility, which is due to the rough SiC-SiO2 interface. The findings also show that a thermally grown SiO2 layer at the semiconductor-dielectric interface is a beneficial process step that enhances the interfacial characteristics and increases the channel mobility of the MOSFETs. In addition to this it is also found that this technique provides the most beneficial characteristics on both n-type and p-type 4H-SiC, which suggests that it would be the most suitable treatment for a monolithic CMOS process. The impact of threshold voltage adjust ion implantation on both the MIS capacitor and MOSFET structures is also presented and shows that the increasing doses of nitrogen that are implanted to adjust the threshold voltage act to improve the device performance by acting to modify the charge at the interface or within the gate oxide and therefore increase the field effect mobility of the studied devices.Engineering and Physical Sciences Research Council (EPSRC) and Raytheon U

Physics and Technology of Silicon Carbide Devices

Recently, some SiC power devices such as Schottky-barrier diodes (SBDs), metal-oxide-semiconductor field-effect-transistors (MOSFETs), junction FETs (JFETs), and their integrated modules have come onto the market. However, to stably supply them and reduce their cost, further improvements for material characterizations and those for device processing are still necessary. This book abundantly describes recent technologies on manufacturing, processing, characterization, modeling, and so on for SiC devices. In particular, for explanation of technologies, I was always careful to argue physics underlying the technologies as much as possible. If this book could be a little helpful to progress of SiC devices, it will be my unexpected happiness

Strain-Engineered MOSFETs

This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization

Conception et fabrication de FinFET GaN verticaux de puissance normalement bloqués

Abstract: The tremendous demands for high-performance systems driven by economic constraints forced the semiconductor industry to considerably scale the device's dimensions to compensate for the relatively modest Silicon physical properties. Those limitations pave the way for III-V semiconductors, which are excellent alternatives to Silicon and can be declined in many compositions. For example, Gallium Nitride (GaN) has been considered a fabulous competitor to facilitate the semiconductor industry's horizon beyond the performance limitations of Silicon due to its high mobility, wide bandgap, and high thermal conductivity properties for T>300K (Bulk GaN). It promises to trim the losses in power conversion circuits and drive a 10 % reduction in power consumption. Both lateral and vertical structures have been considered for GaN power devices. The AlGaN/GaN HEMT device's immense potential comes from the high density, high mobility electron gas formed at its heterojunction. The device is vulnerable to reliability issues resulting from the frequent exposure to high electric field collapse, temperature, and stress conditions, thus limiting its performance and reliability. Contrariwise, the vertical GaN power devices have attracted much attention because of the potential to reach high voltage and current levels without enlarging the chip's size. Furthermore, such vertical devices show superior thermal performance to their lateral counterparts. Meanwhile, Vertical GaN devices have the challenges of high leakage current and the breakdown occurring at the corners of the channel. Another challenge associated with Normally off devices is the lack of an optimized method for eliminating the magnesium diffusion from the p-GaN layer. This thesis has two strategic objectives; Firstly, a Normally-OFF GaN Power FinFET has been designed and optimized to overcome the vertical GaN FinFET challenges. It was done by optimizing the performance parameters such as threshold voltage VTH, high breakdown VBR, and the specific ON-state-resistance RON. Accordingly, the impact of both structural and physical parameters should be incorporated to have an exact optimization process. Afterward, the identification and optimization of a low-cost and high-quality fabrication process for the proposed structure underlined this thesis as the second objective.Les énormes demandes de systèmes à hautes performances motivées par des contraintes économiques ont forcé l'industrie des semi-conducteurs à réduire considérablement les dimensions des dispositifs pour compenser les propriétés physiques relativement modestes du silicium. Ces limitations ouvrent la voie aux semi-conducteurs III-V, qui sont d'excellentes alternatives au silicium et peuvent être déclinés dans de nombreuses compositions. Par exemple, le nitrure de gallium (GaN) a été considéré comme un concurrent fabuleux pour faciliter l'horizon de l'industrie des semi-conducteurs au-delà des limitations de performances du silicium en raison de sa grande mobilité, de sa large bande interdite et de ses propriétés de conductivité thermique élevées pour T>300K (Bulk GaN). Il promet de réduire les pertes dans les circuits de conversion de puissance et de réduire de 10 % la consommation d'énergie. À l'heure actuelle, les structures latérales et verticales ont été considérées pour les dispositifs de puissance en GaN. L'immense potentiel du dispositif HEMT AlGaN/GaN provient du gaz d'électrons à haute densité et à haute mobilité formé au niveau de son hétérojonction. Le dispositif est vulnérable aux problèmes de fiabilité résultant de l'exposition fréquente à des conditions d'effondrement de champ électrique, de température et de contrainte élevés, limitant ainsi ses performances et sa fiabilité. En revanche, les dispositifs de puissance verticaux en GaN ont attiré beaucoup d'attention en raison de leur capacité à atteindre des niveaux de tension et de courant élevés sans augmenter la taille de la puce. De plus, ces dispositifs verticaux présentent des performances thermiques supérieures à leurs homologues latéraux. Par ailleurs, les dispositifs GaN verticaux sont confrontés aux défis d'un courant de fuite élevée et de claquage se produisant aux coins du canal. Un autre défi associé aux dispositifs normalement bloqués est l'absence d'une méthode optimisée pour éliminer la diffusion de magnésium de la couche p-GaN. Cette thèse a deux objectifs stratégiques ; premièrement, un dispositif de puissance FinFET GaN normalement bloqué a été conçu et optimisé pour surmonter les défis du FinFET vertical en GaN. Cela a été fait en optimisant les paramètres de performance tels que la tension de seuil VTH, la tension de claquage VBR et la résistance spécifique à l'état passant RON. En conséquence, l'impact des paramètres structurels et physiques doit être incorporé pour avoir un processus d'optimisation précis. Par la suite, l'identification et l'optimisation d'un processus de fabrication à faible coût et de haute qualité pour la structure proposée à souligner cette thèse comme deuxième objectif

Feature Papers in Electronic Materials Section

This book entitled "Feature Papers in Electronic Materials Section" is a collection of selected papers recently published on the journal Materials, focusing on the latest advances in electronic materials and devices in different fields (e.g., power- and high-frequency electronics, optoelectronic devices, detectors, etc.). In the first part of the book, many articles are dedicated to wide band gap semiconductors (e.g., SiC, GaN, Ga2O3, diamond), focusing on the current relevant materials and devices technology issues. The second part of the book is a miscellaneous of other electronics materials for various applications, including two-dimensional materials for optoelectronic and high-frequency devices. Finally, some recent advances in materials and flexible sensors for bioelectronics and medical applications are presented at the end of the book

Characterization of ultrathin gate dielectrics and multilayer charge injection barriers

Since the invention of the first integrated circuit, the semiconductor industry has distinguished itself by a phenomenally rapid pace of improvements in device performance. This trend of ever smaller and faster devices is a result of the ability to exponentially reduce feature sizes of integrated circuits, a trend commonly known as scaling . A reduction of overall feature sizes requires a simultaneous reduction in the thickness of the gate dielectric, SiO2, of a MOSFET. Gate oxides in the ultrathin regime (\u3c35 A) feature a large direct tunneling leakage current. The presence of this leakage current requires a reevaluation of standard characterization techniques as well as a reevaluation of the continued usefulness of SiO2 as the gate dielectric of choice for future applications. On the other hand, a thorough understanding of the dynamics of ultrathin oxides opens up a range of future device applications that were not possible with thicker oxides. Capacitance-voltage characterization has been the standard technique to study the electrical properties and interface quality of MOS devices. However, the presence of a large leakage current in ultrathin oxides distorts standard C-V measurements, rendering this technique no longer useful. In this work, a leakage compensated charge measurement is developed to overcome this difficulty. This technique produces static C-V curves, even for oxides as thin as 24 A, thereby permitting C-V characterization well into the direct tunneling regime. As an extension of this leakage problem, the usefulness of SiO2 as the gate dielectric of choice for future CMOS devices has been called into question. One solution - but not the only - calls for a new dielectric to replace SiO2 for future gate applications. This research presents some of the earliest results ever on the electrical properties of MOCVD and ALCVD hafnium oxides as a potential candidate. Electrical characterization revealed that the devices have characteristics such as large leakage currents, dielectric charging under stress, hysteresis and a large flatband voltage shift that is commonly found in materials such as the one that was investigated in this work. As one example of future device applications that become possible due to the scaling of ultrathin oxides, silicon-based multilayer charge injection barriers have been investigated. These barriers consist of alternating layers of ultrathin SiO2 and Si. The electrical properties of these structures were studied in detail and revealed that they can be used as an active tunnel dielectric in nonvolatile memory devices

Investigation of the electrical properties of Si₁-xGex channel pMOSFETs with high-κ dielectrics

It is now apparent that the continued performance enhancements of silicon metal-oxide-semiconductor field effect transistors (MOSFETs) can no longer be met by scaling alone. High-mobility channel materials such as strained Si1-xGex and Ge are now being seriously considered to maintain the performance requirements specified by the semiconductor industry. In addition, alternative gate dielectric, or high-? dielectrics, will also be required to meet gate leakage requirements. This work investigates the properties of using strained Si1-xGex or Ge as alternative channel materials for pMOSFETs incorporating hafnium oxide (HfO2) high-? gate dielectric. Whilst the SiGe pMOSFETs (x = 0.25) exhibited an enhancement in hole mobility (300 K) over comparable silicon control pMOSFETs with sputtered HfO2 dielectric, high Coulomb scattering and surface roughness scattering relating to the dielectric deposition process meant that the effective hole mobilities were degraded with respect to the silicon universal curve. Germanium channel pMOSFETs with halo-doping and HfO2 gate dielectric deposited by atomic layer deposition showed high hole mobilities of 230 cm2V-1s-1 and 480 cm2V-1s-1 at room temperature and 77 K, respectively. Analysis of the off-state current for the Ge pMOSFETs over a range of temperatures indicated that band-to-band tunnelling, gate-induced drain leakage and other defect-assisted leakage mechanisms could all be important. Hole carrier velocity and impact ionisation were also studied in two batches of buried channel SiGe pMOSFET with x = 0.15 and x = 0.36, respectively. SiGe channel pMOSFETs were found to exhibit reduced impact ionisation compared to silicon control devices, which has been attributed to a strain-induced reduction of the density of states in the SiGe conduction and valence bands. Analysis of the hole carrier velocity indicated that pseudomorphic SiGe offered no performance enhancements over Si below 100 nm, possibly due to higher ion implantation damage and strain relaxation of the strained SiGe channel. The results indicate that velocity overshoot effects might not provide the performance improvements at short channel lengths that was previously hoped for.EThOS - Electronic Theses Online ServiceGBUnited Kingdo