Oxygen-insertion Technology for CMOS Performance Enhancement

Until 2003, the semiconductor industry followed Dennard scaling rules to improve complementary metal-oxide-semiconductor (CMOS) transistor performance. However, performance gains with further reductions in transistor gate length are limited by physical effects that do not scale commensurately with device dimensions: short-channel effects (SCE) due to gate-leakage-limited gate-oxide thickness scaling, channel mobility degradation due to enhanced vertical electric fields, increased parasitic resistances due to reductions in source/drain (S/D) contact area, and increased variability in transistor performance due to random dopant fluctuation (RDF) effects and gate work function variations (WFV). These emerging scaling issues, together with increased process complexity and cost, pose severe challenges to maintaining the exponential scaling of transistor dimensions. This dissertation discusses the benefits of oxygen-insertion (OI) technology, a CMOS performance booster, for overcoming these challenges. The benefit of OI technology to mitigate the increase in sheet resistance ($R_{sh}$) with decreasing junction depth ($X_J$) for ultra-shallow-junctions (USJs) relevant for deep-sub-micron planar CMOS transistors is assessed through the fabrication of $R_{sh}$ test structures, electrical characterization, and technology computer-aided design (TCAD) simulations. Experimental and secondary ion mass spectroscopy (SIMS) analyses indicate that OI technology can facilitate low-resistivity USJ formation by reducing $R_{sh}$ and $X_J$ due to retarded transient-enhanced-diffusion (TED) effects and enhanced dopant retention during post-implantation thermal annealing. It is also shown that a low-temperature-oxide (LTO) capping can increase $R_{sh}$ unfavorably due to lower dopant activation levels, which can be alleviated by OI technology. This dissertation extends the evaluation of OI technology to advanced FinFET technology, targeting 7/8-nm low power technology node. A bulk-Si FinFET design comprising a super-steep retrograde (SSR) fin channel doping profile achievable with OI technology is studied by three-dimensional (3-D) TCAD simulations. As compared with the conventional bulk-Si (control) FinFET design with a heavily-doped fin channel doping profile, SSR FinFETs can achieve higher $I_{on}/I_{off}$ ratios and reduce the sensitivity of device performance to variations due to the lightly doped fin channel. As compared with the SOI FinFET design, SSR FinFETs can achieve similarly low $V_{DD,min}$ for 6T-SRAM cell yield estimation. Both SSR and SOI design can provide for as much as 100 mV reduction in $V_{DD,min}$ compared with the control FinFET design. Overall, the SSR FinFET design that can be achieved with OI technology is demonstrated to be a cheaper alternative to the SOI FinFET technology for extending CMOS scaling beyond the 10-nm node. Finally, this dissertation investigates the benefits of OI technology for reducing the Schottky barrier height ($\Phi_{Bp}$) of a Pt/Ti/p-type Si metal-semiconductor (M/S) contact, which can be expected to help reduce the specific contact resistivity for a p-type silicon contact. Electrical measurements of back-to-back Schottky diodes, SIMS, and X-ray photoelectron spectroscopy (XPS) show that the reduction in $\Phi_{Bp}$ is associated with enhanced Ti 2p and Si 2p core energy level shifts. OI technology is shown to favor low-$\Phi_{Bp}$ Pt monosilicide formation during forming gas anneal (FGA) by suppressing the grain boundary diffusion of Pt atoms into the crystalline Si substrate

On Energy Efficient Computing Platforms

In accordance with the Moore's law, the increasing number of on-chip integrated transistors has enabled modern computing platforms with not only higher processing power but also more affordable prices. As a result, these platforms, including portable devices, work stations and data centres, are becoming an inevitable part of the human society. However, with the demand for portability and raising cost of power, energy efficiency has emerged to be a major concern for modern computing platforms. As the complexity of on-chip systems increases, Network-on-Chip (NoC) has been proved as an efficient communication architecture which can further improve system performances and scalability while reducing the design cost. Therefore, in this thesis, we study and propose energy optimization approaches based on NoC architecture, with special focuses on the following aspects. As the architectural trend of future computing platforms, 3D systems have many bene ts including higher integration density, smaller footprint, heterogeneous integration, etc. Moreover, 3D technology can signi cantly improve the network communication and effectively avoid long wirings, and therefore, provide higher system performance and energy efficiency. With the dynamic nature of on-chip communication in large scale NoC based systems, run-time system optimization is of crucial importance in order to achieve higher system reliability and essentially energy efficiency. In this thesis, we propose an agent based system design approach where agents are on-chip components which monitor and control system parameters such as supply voltage, operating frequency, etc. With this approach, we have analysed the implementation alternatives for dynamic voltage and frequency scaling and power gating techniques at different granularity, which reduce both dynamic and leakage energy consumption. Topologies, being one of the key factors for NoCs, are also explored for energy saving purpose. A Honeycomb NoC architecture is proposed in this thesis with turn-model based deadlock-free routing algorithms. Our analysis and simulation based evaluation show that Honeycomb NoCs outperform their Mesh based counterparts in terms of network cost, system performance as well as energy efficiency.Siirretty Doriast

Multiprocessor System-on-Chips based Wireless Sensor Network Energy Optimization

Wireless Sensor Network (WSN) is an integrated part of the Internet-of-Things (IoT) used to monitor the physical or environmental conditions without human intervention. In WSN one of the major challenges is energy consumption reduction both at the sensor nodes and network levels. High energy consumption not only causes an increased carbon footprint but also limits the lifetime (LT) of the network. Network-on-Chip (NoC) based Multiprocessor System-on-Chips (MPSoCs) are becoming the de-facto computing platform for computationally extensive real-time applications in IoT due to their high performance and exceptional quality-of-service. In this thesis a task scheduling problem is investigated using MPSoCs architecture for tasks with precedence and deadline constraints in order to minimize the processing energy consumption while guaranteeing the timing constraints. Moreover, energy-aware nodes clustering is also performed to reduce the transmission energy consumption of the sensor nodes. Three distinct problems for energy optimization are investigated given as follows: First, a contention-aware energy-efficient static scheduling using NoC based heterogeneous MPSoC is performed for real-time tasks with an individual deadline and precedence constraints. An offline meta-heuristic based contention-aware energy-efficient task scheduling is developed that performs task ordering, mapping, and voltage assignment in an integrated manner. Compared to state-of-the-art scheduling our proposed algorithm significantly improves the energy-efficiency. Second, an energy-aware scheduling is investigated for a set of tasks with precedence constraints deploying Voltage Frequency Island (VFI) based heterogeneous NoC-MPSoCs. A novel population based algorithm called ARSH-FATI is developed that can dynamically switch between explorative and exploitative search modes at run-time. ARSH-FATI performance is superior to the existing task schedulers developed for homogeneous VFI-NoC-MPSoCs. Third, the transmission energy consumption of the sensor nodes in WSN is reduced by developing ARSH-FATI based Cluster Head Selection (ARSH-FATI-CHS) algorithm integrated with a heuristic called Novel Ranked Based Clustering (NRC). In cluster formation parameters such as residual energy, distance parameters, and workload on CHs are considered to improve LT of the network. The results prove that ARSH-FATI-CHS outperforms other state-of-the-art clustering algorithms in terms of LT.University of Derby, Derby, U

Circuits and Systems Advances in Near Threshold Computing

Modern society is witnessing a sea change in ubiquitous computing, in which people have embraced computing systems as an indispensable part of day-to-day existence. Computation, storage, and communication abilities of smartphones, for example, have undergone monumental changes over the past decade. However, global emphasis on creating and sustaining green environments is leading to a rapid and ongoing proliferation of edge computing systems and applications. As a broad spectrum of healthcare, home, and transport applications shift to the edge of the network, near-threshold computing (NTC) is emerging as one of the promising low-power computing platforms. An NTC device sets its supply voltage close to its threshold voltage, dramatically reducing the energy consumption. Despite showing substantial promise in terms of energy efficiency, NTC is yet to see widescale commercial adoption. This is because circuits and systems operating with NTC suffer from several problems, including increased sensitivity to process variation, reliability problems, performance degradation, and security vulnerabilities, to name a few. To realize its potential, we need designs, techniques, and solutions to overcome these challenges associated with NTC circuits and systems. The readers of this book will be able to familiarize themselves with recent advances in electronics systems, focusing on near-threshold computing

CMOS 소자와 함께 쓸 수 있는 실리콘 나노선 터널링 전계효과 트랜지스터

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 박병국.향후 CMOS 기술의 축소화에 따른 소자의 소비전력증가 문제를 해결하고 0.5 V 이하의 동작전압으로도 저전력 동작하는 스위칭 소자를 개발하기 위해, 기존 CMOS 기술을 변형한 집적방법으로 실리콘 나노와이어 밴드간-터널링 전계효과 트랜지스터(band-to-band tunneling field-effect transistorTFET)와 금속-산화막-반도체 전계효과 트랜지스터(metal-oxide-semiconductor field-effect transistorMOSFET)를 동시집적하고 소자로써 동작을 확인하였다. TFET은 동작원리상 소스 영역의 에너지의 상한 값이 제한되어 있는 가전자대의 전자가 터널링에 의해 캐리어가 채널로 주입되므로 상온에서 MOSFET 보다 훨씬 작은 게이트 전압변화로 소자를 켤 수 있는 특징이 있다. 이 소자에서 터널링을 촉진하려면 소스/채널간 접합을 적은 공핍에도 쉽게 켤 수 있어야 하므로 게이트 산화막의 두께, 나노와이어의 선폭, 측벽 스페이서의 폭이 작아야 하고 접합주변에서 불순물 농도가 급격히 변해야 함을 이론적인 TCAD 시뮬레이션 연구를 통해 알 수 있었다. 이론적 연구를 바탕으로, 소스와 드레인의 극성이 서로 다른 TFET을 집적하기 위해 기존의 CMOS 집적방법에 자가정렬 비대칭 소스/드레인을 형성하는 집적방법 (integration scheme for self-aligned asymmetric source/drain)을 추가하여 MOSFET과 TFET을 SOI 기판 위에 동시집적 하였다. 최적화된 전자선 리소그래피공정 (electron-beam lithography)과 새로 개발한 화학적 코너 라운딩 (chemical corner-rounding) 방법을 적용하여 최소 선폭 14.5 nm의 반실린더형 나노와이어를 성공적으로 형성하였다. 측벽 스페이서는 질화막과 산화막으로 폭 20 nm로 형성하여, 액티브 영역의 손상을 최소화하여 자가정렬된 니켈 실리사이드 (self-aligned nickel silicide)를 형성하는데 문제가 없도록 하면서도 측벽 스페이서의 선폭을 최소화할 수 있도록 하였다. 접합의 농도가 급변하게 하기 위해서 니켈 실리사이드에 의한 스노플라우 효과 (snowploughing effect)를 이용하였다. 이를 통해 게이트 길이 1 μm인 장채널 TFET과 150 ~ 28 nm의 단채널 TFET들이 자기정렬 방식으로 성공적으로 제작되었다. 제작된 소자의 측정결과 n+/진성 경계가 p+/진성 경계에서보다 불순물 농도가 더 급격하도록 만들어진 것을 확인하였고, 따라서 TFET은 p-채널 모드로 더 잘 동작하였다. 장채널소자에서는 순간기울기 기준 47 mV/decade 로 동작하는 소자가 만들어진 것을 확인하였으며, 단채널 TFET으로는 MOSFET의 경우처럼 채널길이가 짧아질 수록 게이트의 채널제어능력이 나빠지는 단채널효과가 TFET에도 존재함을 확인하였다. 단채널효과는 나노와이어의 선폭이 작아진 경우 감소하였는데 나노와이어 선폭 19.5 nm이고 게이트 선폭이 109 nm인 소자에서 62 mV/decade의 양호한 TFET 동작특성을 보였다. 이와 더불어 채널방향에 따른 소자 특성개선 가능성과 반실린더형 채널구조를 이용한 기판전압에 의한 소자특성 조절에 대한 가능성을 제작된 소자로부터 검토하였다. 이상의 결과에서 기존 CMOS 기술을 변형하는 방식으로 MOSFET과 TFET을 동시집적함으로써 좀 더 양산가능성 높은 TFET 제작 방법을 제시 하였으며 향후 MOSFET-TFET 혼성회로를 이용한 미래 CMOS 회로의 저전력화 가능성을 제시하였다.In order to develop practical low-power switching devices operating at a voltage below 0.5 V and solve the power density problem of highly-scaled CMOS technology, the silicon nanowire band-to-band tunneling field-effect transistors (TFETs) and conventional metal-oxide-semiconductor field-effect transistors (MOSFETs) are co-integrated with a modified CMOS flow and their electrical functionalities are confirmed. Since the carrier injection in a TFET system occurs by tunneling of valence-band electrons, it can operate without leakage issue and the gate bias swing to switch the device can be very small. In spite of the fancy operating principles, however, the replacement of MOSFETs with TFETs is not likely to happen in near future. This is because the difference of source/drain (S/D) polarities and current-flow directionality issues make TFETs not suitable for the existing MOSFET-based CMOS circuits but demanding new circuit topologies. Therefore the TFETs that can be co-integrated with MOSFETs are selected as the topic of this work. From the theoretical study with a TCAD device simulator, the gate insulator thickness, nanowire width, abruptness of doping profile near the source/channel boundary and the design of sidewall spacer width are found to be critical to reducing the tunneling barrier width to increase the current. Design concepts learned from TCAD simulation studies are implemented to fabrication with a novel integration scheme for self-aligned asymmetric S/D. By inserting the process steps to form the asymmetric S/D to the conventional CMOS process flow, MOSFETs and TFETs are successfully co-integrated on the same silicon-on-insulator substrate. Through newly developed and optimized processes such as reduced-repulsion electron-beam lithography, chemical corner-rounding, tight sidewall spacer etch, and two-step self-aligned nickel silicide process, the TFETs with L = 1 μm ~ 28 nm, minimum W = 14.5 nm, 20 nm dual sidewall spacer, and dopant-segregated steep doping profile are successfully fabricated. From the electrical measurement of gate-induced drain leakage (GIDL) of the co-integrated MOSFETs, the impurity profile near the n+/intrinsic boundary is found to be much more abrupt than near p+/intrinsic boundary. Therefore, the fabricated TFETs operate better as a p-channel device rather than n-channel device. The long-channel device shows good switching characteristics of 47 mV/decade. Short-channel effect similar to that of MOSFETs is experimentally observed for TFETs. It is also demonstrated that the short-channel effect can be reduced by improving electrostatics, with a thinner-nanowire device with L = 109 nm. Substrate-bias controllability of TFETs and its extension to nanowire TFETs are examined in the comparison with MOSFETs. Possibilities to improve current drivability by controlling tunneling process with the channel direction are explored with both planar and nanowire TFETs. From this study, it is demonstrated that TFETs can be co-integrated with CMOS devices in a more manufacturable way by introducing a self-aligned integration scheme to conventional process flow. This work also opens a possibility of a new low-power design technology using MOSFET/TFET hybrid circuits.Chapter 1 Introduction 1 1.1 Origin of Power Crisis in CMOS Technologies .......................... 1 1.2 Tunneling Field-Effect Transistors (TFETs) ............................... 3 1.3 Replacer or Complementor? ....................................................... 5 1.4 Previous Studies .......................................................................... 7 1.5 Thesis Outline ............................................................................. 9 Chapter 2 Theoretical Studies 11 2.1 Basic Operations of TFETs ....................................................... 11 2.2 Nanowire TFETs ...................................................................... 15 2.3 Device Design Factors and Variability ..................................... 17 2.4 Operation Range Where TFETs Beat MOSFETs ..................... 25 2.5 Summary of the Target Device ................................................. 27 Chapter 3 Device Fabrication 29 3.1 Key Process Designs and Fabrication Flow ............................. 29 3.2 Patterning and Rounding of Nanowire Active Regions ........... 31 3.3 Self-aligned Formation of Gate and Asymmetric S/D Regions 35 3.4 Sidewall Spacer and Self-aligned Silicide Processes................ 38 Chapter 4 Device Characteristics 42 4.1 Fabricated Metal-Oxide-Semiconductor Capacitor ................. 42 4.2 Junction Properties of Co-Integrated MOSFETs ...................... 44 4.3 Transfer and Output Characteristics of TFETs ......................... 48 4.4 Device Properties with Design Partitionings ........................... 54 4.4.1 Active Width .............................................................. 54 4.4.2 Channel Length .......................................................... 55 4.4.3 Channel Direction ...................................................... 60 4.4.4 Back-Gate Effect ........................................................ 64   Chapter 5 Conclusions 67 5.1 Conclusions .............................................................................. 67 5.2 Suggestions for Future Work .................................................. 69 Bibliography....................................................................... 71 Appendixes ......................................................................... 82 Abstract in Korean ............................................................ 87 Acknowledgements ............................................................ 90Docto

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

Integrated Circuits Parasitic Capacitance Extraction Using Machine Learning and its Application to Layout Optimization

The impact of parasitic elements on the overall circuit performance keeps increasing from one technology generation to the next. In advanced process nodes, the parasitic effects dominate the overall circuit performance. As a result, the accuracy requirements of parasitic extraction processes significantly increased, especially for parasitic capacitance extraction. Existing parasitic capacitance extraction tools face many challenges to cope with such new accuracy requirements that are set by semiconductor foundries (\u3c 5% error). Although field-solver methods can meet such requirements, they are very slow and have a limited capacity. The other alternative is the rule-based parasitic capacitance extraction methods, which are faster and have a high capacity; however, they cannot consistently provide good accuracy as they use a pre-characterized library of capacitance formulas that cover a limited number of layout patterns. On the other hand, the new parasitic extraction accuracy requirements also added more challenges on existing parasitic-aware routing optimization methods, where simplified parasitic models are used to optimize layouts. This dissertation provides new solutions for interconnect parasitic capacitance extraction and parasitic-aware routing optimization methodologies in order to cope with the new accuracy requirements of advanced process nodes as follows. First, machine learning compact models are developed in rule-based extractors to predict parasitic capacitances of cross-section layout patterns efficiently. The developed models mitigate the problems of the pre-characterized library approach, where each compact model is designed to extract parasitic capacitances of cross-sections of arbitrary distributed metal polygons that belong to a specific set of metal layers (i.e., layer combination) efficiently. Therefore, the number of covered layout patterns significantly increased. Second, machine learning compact models are developed to predict parasitic capacitances of middle-end-of-line (MEOL) layers around FINFETs and MOSFETs. Each compact model extracts parasitic capacitances of 3D MEOL patterns of a specific device type regardless of its metal polygons distribution. Therefore, the developed MEOL models can replace field-solvers in extracting MEOL patterns. Third, a novel accuracy-based hybrid parasitic capacitance extraction method is developed. The proposed hybrid flow divides a layout into windows and extracts the parasitic capacitances of each window using one of three parasitic capacitance extraction methods that include: 1) rule-based; 2) novel deep-neural-networks-based; and 3) field-solver methods. This hybrid methodology uses neural-networks classifiers to determine an appropriate extraction method for each window. Moreover, as an intermediate parasitic capacitance extraction method between rule-based and field-solver methods, a novel deep-neural-networks-based extraction method is developed. This intermediate level of accuracy and speed is needed since using only rule-based and field-solver methods (for hybrid extraction) results in using field-solver most of the time for any required high accuracy extraction. Eventually, a parasitic-aware layout routing optimization and analysis methodology is implemented based on an incremental parasitic extraction and a fast optimization methodology. Unlike existing flows that do not provide a mechanism to analyze the impact of modifying layout geometries on a circuit performance, the proposed methodology provides novel sensitivity circuit models to analyze the integrity of signals in layout routes. Such circuit models are based on an accurate matrix circuit representation, a cost function, and an accurate parasitic sensitivity extraction. The circuit models identify critical parasitic elements along with the corresponding layout geometries in a certain route, where they measure the sensitivity of a route’s performance to corresponding layout geometries very fast. Moreover, the proposed methodology uses a nonlinear programming technique to optimize problematic routes with pre-determined degrees of freedom using the proposed circuit models. Furthermore, it uses a novel incremental parasitic extraction method to extract parasitic elements of modified geometries efficiently, where the incremental extraction is used as a part of the routing optimization process to improve the optimization runtime and increase the optimization accuracy

높은 구동 전류와 낮은 문턱전압 이하 스윙을 가지는 L자 형태의 터널링 전계효과 트랜지스터

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 박병국.In order to solve power crisis in highly-scaled CMOS technology, a novel tunnel field-effect transistors (TFETs), named L-shaped TFETs, have been proposed and its electrical properties are examined. It features band-to-band tunneling (BTBT) direction parallel to the normal electric field induced by gate electrode. Because carrier injection is occurred perpendicular to the channel direction, cross-sectional area and barrier width of BTBT junction could be defined by structural parameters. Using the commercial TCAD device simulator, its electrical characteristics are examined and optimized. It is expected that the L-shaped TFETs will reveal better performance than conventional ones in terms of subthreshold swing (S), on-current (Ion) and short channel effect. In addition, the performance of L-shaped TFET inverters has been compared with that of conventional TFET ones for its complementary logic application. After the key process techniques are obtained, control and comparison samples are fabricated at Inter-University Semiconductor Research Center (ISRC) of Seoul National University (SNU), Korea. The main process technique is as follow: in-situ doped epitaxial layer growth for constantly doped source region, selective epitaxial layer growth of silicon at low temperature for tunneling region, and guarantee sub-3-nm gate dielectric. From the electrical measurement of transfer and output characteristics, it is verified that 102 mV/dec minimum S in conventional TFET is improve to 7, 34 and 59 mV/dec in L-shaped TFET. In addition, the Ion of L-shaped TFET is more than 10 times larger than that of conventional one. Extracting several parameters such as source/drain resistance, channel resistance, mobility, and tunneling resistance, it is clear that the improved performance comes from the reduction of tunneling resistance. From this study, it is demonstrated that L-shaped TFET will be one of the most promising candidate for a next-generation low-power device.Abstract i Contents iii List of Tables v List of Figures vi Chapter 1 Introduction 1 1.1 NECESSITY OF ALTERNATIVES TO CMOS 1 1.2 TUNNEL FIELD-EFFECT TRANSISTORS (TFETS) 4 1.3 TECHNICAL ISSUES OF TFETS 7 1.4 SCOPE OF THESIS 10 Chapter 2 L-shaped TFET 11 2.1 FEATURES OF L-SHAPED TFET 11 2.2 DESIGN OPTIMIZATION 17 2.3 CORNER EFFECT 27 2.4 FURTHER IMPROVEMENT AND CIRCUIT APPLICATION 36 2.5 SUMMARY OF TARGET DEVICE 40 Chapter 3 Device Fabrication 42 3.1 FABRICATION OF CONTROL TFETS 42 3.2 KEY PROCESS DESIGNS FOR L-SHAPED TFETS 45 3.3 FABRICATION OF L-SHAPED TFET 51 3.4 SIDEWALL SPACER FOR MINIMIZATION OF MIS-ALIGNMENT 56 Chapter 4 Device Characteristics 59 4.1 METAL-OXIDE-SEMICONDUCTOR (MOS) CAPACITOR 59 4.2 CONTROL SAMPLES OF CONVENTIONAL PLANAR TFETS 63 4.3 L-SHAPED TFETS 71 4.4 EXTRACTION OF SEVERAL ELECTRICAL PARAMETERS 76 Chapter 5 80 Conclusions 80 Bibliography 82 Abstract in Korean 89 Curriculum Vitae 91Docto

Design of variation-tolerant synchronizers for multiple clock and voltage domains

PhD ThesisParametric variability increasingly affects the performance of electronic circuits as the fabrication technology has reached the level of 32nm and beyond. These parameters may include transistor Process parameters (such as threshold voltage), supply Voltage and Temperature (PVT), all of which could have a significant impact on the speed and power consumption of the circuit, particularly if the variations exceed the design margins. As systems are designed with more asynchronous protocols, there is a need for highly robust synchronizers and arbiters. These components are often used as interfaces between communication links of different timing domains as well as sampling devices for asynchronous inputs coming from external components. These applications have created a need for new robust designs of synchronizers and arbiters that can tolerate process, voltage and temperature variations. The aim of this study was to investigate how synchronizers and arbiters should be designed to tolerate parametric variations. All investigations focused mainly on circuit-level and transistor level designs and were modeled and simulated in the UMC90nm CMOS technology process. Analog simulations were used to measure timing parameters and power consumption along with a “Monte Carlo” statistical analysis to account for process variations. Two main components of synchronizers and arbiters were primarily investigated: flip-flop and mutual-exclusion element (MUTEX). Both components can violate the input timing conditions, setup and hold window times, which could cause metastability inside their bistable elements and possibly end in failures. The mean-time between failures is an important reliability feature of any synchronizer delay through the synchronizer. The MUTEX study focused on the classical circuit, in addition to a number of tolerance, based on increasing internal gain by adding current sources, reducing the capacitive loading, boosting the transconductance of the latch, compensating the existing Miller capacitance, and adding asymmetry to maneuver the metastable point. The results showed that some circuits had little or almost no improvements, while five techniques showed significant improvements by reducing τ and maintaining high tolerance. Three design approaches are proposed to provide variation-tolerant synchronizers. wagging synchronizer proposed to First, the is significantly increase reliability over that of the conventional two flip-flop synchronizer. The robustness of the wagging technique can be enhanced by using robust τ latches or adding one more cycle of synchronization. The second approach is the Metastability Auto-Detection and Correction (MADAC) latch which relies on swiftly detecting a metastable event and correcting it by enforcing the previously stored logic value. This technique significantly reduces the resolution time down from uncertain synchronization technique is proposed to transfer signals between Multiple- Voltage Multiple-Clock Domains (MVD/MCD) that do not require conventional level-shifters between the domains or multiple power supplies within each domain. This interface circuit uses a synchronous set and feedback reset protocol which provides level-shifting and synchronization of all signals between the domains, from a wide range of voltage-supplies and clock frequencies. Overall, synchronizer circuits can tolerate variations to a greater extent by employing the wagging technique or using a MADAC latch, while MUTEX tolerance can suffice with small circuit modifications. Communication between MVD/MCD can be achieved by an asynchronous handshake without a need for adding level-shifters.The Saudi Arabian Embassy in London, Umm Al-Qura University, Saudi Arabi