Tuning ultrafast electron thermalization pathways in a van der Waals heterostructure

Ultrafast electron thermalization - the process leading to Auger recombination, carrier multiplication via impact ionization and hot carrier luminescence - occurs when optically excited electrons in a material undergo rapid electron-electron scattering to redistribute excess energy and reach electronic thermal equilibrium. Due to extremely short time and length scales, the measurement and manipulation of electron thermalization in nanoscale devices remains challenging even with the most advanced ultrafast laser techniques. Here, we overcome this challenge by leveraging the atomic thinness of two-dimensional van der Waals (vdW) materials in order to introduce a highly tunable electron transfer pathway that directly competes with electron thermalization. We realize this scheme in a graphene-boron nitride-graphene (G-BN-G) vdW heterostructure, through which optically excited carriers are transported from one graphene layer to the other. By applying an interlayer bias voltage or varying the excitation photon energy, interlayer carrier transport can be controlled to occur faster or slower than the intralayer scattering events, thus effectively tuning the electron thermalization pathways in graphene. Our findings, which demonstrate a novel means to probe and directly modulate electron energy transport in nanoscale materials, represent an important step toward designing and implementing novel optoelectronic and energy-harvesting devices with tailored microscopic properties.Comment: Accepted to Nature Physic

Characterization of the Si/SiO2 interface morphology from quantum oscillations in Fowler–Nordheim tunneling currents

As design rules shrink to conform with ULSI device dimensions, gate dielectrics for MOSFET structures are required to be scaled to below ~60A where some properties of the device, such as interface roughness, that are negligible for thicker films become critical. Microroughness at the interface of ultrathin MOS capacitors has been shown to degrade these devices. The present study focuses on the interfacial region of -50A. SiO, on Si, using the quantum oscillations in Fowler-Nordheim tunneling currents as a probe. The oscillations are sensitive to the electron potential and abruptness of the film and interfaces. In particular, inelastic scattering and/or thickness inhomogeneities in the film will reduce the amplitude of the oscillations. We are using the amplitude of the oscillations to examine the degree of microroughness at the interface that results from a pre-oxidation high temperature anneal in an inert ambient containing various amounts of H20. AFM imaging has shown correlations supporting a microroughness induced change in the quantum oscillation amplitudes

Synthesis of silicon nanocrystal memories by sputter deposition

In Silizium-Nanokristall-Speichern werden im Gate-Oxid eines Feldeffekttransistors eingebettete Silizium Nanokristalle genutzt, um Elektronen lokal zu speichern. Die gespeicherte Ladung bestimmt dann den Zustand der Speicherzelle. Ein wichtiger Aspekt in der Technologie dieser Speicher ist die Erzeugung der Nanokristalle mit einerwohldefinierten Größenverteilung und einem bestimmten Konzentrationsprofil im Gate-Oxid. In der vorliegenden Arbeit wurde dazu ein sehr flexibler Ansatz untersucht: die thermische Ausheilung von SiO2/SiOx (x < 2) Stapelschichten. Es wurde ein Sputterverfahren entwickelt, das die Abscheidung von SiO2 und SiOx Schichten beliebiger Zusammensetzung erlaubt. Die Bildung der Nanokristalle wurde in Abhängigkeit vom Ausheilregime und der SiOx Zusammensetzung charakterisiert, wobei unter anderem Methoden wie Photolumineszenz, Infrarot-Absorption, spektroskopische Ellipsometrie und Elektronenmikroskopie eingesetzt wurden. Anhand von MOS-Kondensatoren wurden die elektrischen Eigenschaften derart hergestellter Speicherzellen untersucht. Die Funktionalität der durch Sputterverfahren hergestellten Nanokristall-Speicher wurde erfolgreich nachgewiesen.In silicon nanocrystal memories, electronic charge is discretely stored in isolated silicon nanocrystals embedded in the gate oxide of a field effect transistor. The stored charge determines the state of the memory cell. One important aspect in the technology of silicon nanocrystal memories is the formation of nanocrystals near the SiO2-Si interface, since both, the size distribution and the depth profile of the area density of nanocrystals must be controlled. This work has focussed on the formation of gate oxide stacks with embedded nanocrystals using a very flexible approach: the thermal annealing of SiO2/SiOx (x < 2) stacks. A sputter deposition method allowing to deposit SiO2 and SiOx films of arbitrary composition has been developed and optimized. The formation of Si NC during thermal annealing of SiOX has been investigated experimentally as a function of SiOx composition and annealing regime using techniques such as photoluminescence, infrared absorption, spectral ellipsometry, and electron microscopy. To proof the concept, silicon nanocrystal memory capacitors have been prepared and characterized. The functionality of silicon nanocrystal memory devices based on sputtered gate oxide stacks has been successfully demonstrated

Synthesis of silicon nanocrystal memories by sputter deposition

In Silizium-Nanokristall-Speichern werden im Gate-Oxid eines Feldeffekttransistors eingebettete Silizium Nanokristalle genutzt, um Elektronen lokal zu speichern. Die gespeicherte Ladung bestimmt dann den Zustand der Speicherzelle. Ein wichtiger Aspekt in der Technologie dieser Speicher ist die Erzeugung der Nanokristalle mit einerwohldefinierten Größenverteilung und einem bestimmten Konzentrationsprofil im Gate-Oxid. In der vorliegenden Arbeit wurde dazu ein sehr flexibler Ansatz untersucht: die thermische Ausheilung von SiO2/SiOx (x < 2) Stapelschichten. Es wurde ein Sputterverfahren entwickelt, das die Abscheidung von SiO2 und SiOx Schichten beliebiger Zusammensetzung erlaubt. Die Bildung der Nanokristalle wurde in Abhängigkeit vom Ausheilregime und der SiOx Zusammensetzung charakterisiert, wobei unter anderem Methoden wie Photolumineszenz, Infrarot-Absorption, spektroskopische Ellipsometrie und Elektronenmikroskopie eingesetzt wurden. Anhand von MOS-Kondensatoren wurden die elektrischen Eigenschaften derart hergestellter Speicherzellen untersucht. Die Funktionalität der durch Sputterverfahren hergestellten Nanokristall-Speicher wurde erfolgreich nachgewiesen.In silicon nanocrystal memories, electronic charge is discretely stored in isolated silicon nanocrystals embedded in the gate oxide of a field effect transistor. The stored charge determines the state of the memory cell. One important aspect in the technology of silicon nanocrystal memories is the formation of nanocrystals near the SiO2-Si interface, since both, the size distribution and the depth profile of the area density of nanocrystals must be controlled. This work has focussed on the formation of gate oxide stacks with embedded nanocrystals using a very flexible approach: the thermal annealing of SiO2/SiOx (x < 2) stacks. A sputter deposition method allowing to deposit SiO2 and SiOx films of arbitrary composition has been developed and optimized. The formation of Si NC during thermal annealing of SiOX has been investigated experimentally as a function of SiOx composition and annealing regime using techniques such as photoluminescence, infrared absorption, spectral ellipsometry, and electron microscopy. To proof the concept, silicon nanocrystal memory capacitors have been prepared and characterized. The functionality of silicon nanocrystal memory devices based on sputtered gate oxide stacks has been successfully demonstrated

Large scale tunneling junctions for electrically driven plasmonics

This work focuses on the fabrication of light emitting tunneling junctions in planar configuration comprised of thin-film material stacks analog to metal-insulator-semiconductor plate capacitors. Electrical and structural properties are studied by different experimental techniques (current-voltage analysis, impedance spectroscopy) and compared to existing theories. Assessment of the junction quality is done in comparison to known features of electrically-driven plasmons, such as the bias dependent cut-off frequency, the dependency of the emission intensity on the tunneling current and tuneability of the spectra by implementation of different materials. Enhanced scattering and tuneability of light emission features from tunneling junctions by adsorption of chemically-synthesized nanoparticles is demonstrated and localization of the emission hot spots by correlation with measurements in external illumination and topography scans are discussed. Operational stability is increased by decoupling of the fabrication sub-steps, i.e. deposition of high quality thin-film stacks and chemical synthesis of particles with tailored optical properties. The role of nanoparticle geometry and material as hot spots in light emitting tunneling junctions is described and distinguished to reference experiments with external illumination. Emission instabilities in low-frequency regimes from hot spots with uncorrelated phases have been observed and are discussed. Potential transferability of electrically-driven plasmons to established detection schemes is demonstrated exemplary by mimicking a study of a plasmonic nanoruler. Additionally, a first proof-of-principle study on the emission from light emitting tunneling junctions in direct water immersion is described

Nanodot-based organic memory devices

In this study, resistor-type, diode-type, and transistor-type organic memory devices were investigated, aiming at the low-cost plastic integrated circuit applications. A series of solution-processing techniques including spin-coating, inkjet printing, and self-assembly were employed to fabricate these devices. The organic resistive memory device is based on a novel molecular complex film composed of tetracyanoquinodimethane (TCNQ) and a soluble methanofullerene derivative [6,6]-phenyl C61-butyric acid methyl ester (PCBM). It has an Al/molecules/Al sandwich structure. The molecular layer was formed by spin-coating technique instead of expensive vacuum deposition method. The current-voltage characteristics show that the device switches from the initial \u27low\u27 conduction state to \u27high\u27 conduction state upon application of external electric field at room temperature and return to \u27low\u27 conduction state when a high current pulse is applied. The on/off ratio is over 106. Each state has been found to remain stable for more than five months, even after the external electric field is removed. The PCBM nanodots wrapped by TCNQ molecules can form potential wells for charge trapping, and are believed to be responsible for the memory effects. A rewritable diode memory device was achieved in an improved configuration, i.e., ITO-PEDOT:PSS-PCBM/TCNQ-Al, where a semiconductor polymer PEDOT:PSS is used to form p+-N heterojunction with PCBM/TCNQ. It exhibits a diode characteristic (low conductive) before switching to a high-conductive Poole-Frenkel regime upon applying a positive external bias to ITO. The on/off ratio at +1.0 V is up to 105. Simulation results from Taurus-Medici are in qualitative agreement with the experimental results and the proposed charge storage model. The transistor-type memory device is fabricated on a heavily doped n-type silicon (n+-Si) substrate with a 100 nm thick thermally-grown oxide layer. The n+-Si serves as the gate electrode, while the oxide layer functions as the control gate dielectric. Gold nanoparticles as the charge storage units are deposited on the substrate by electrostatic self-assembly method. A self-assembled multilayer of polyelectrolytes, together with a thin spin-coated poly(4-vinyl phenol) layer, covers the gold nanoparticles and separates them from the poly(3-hexyl thiophene) channel. Conducting polymer PEDOT:PSS is inkjet printed to form the source/drain electrodes. The device exhibits significant hysteresis behavior in its Ids-Vgs characteristics. The charge storage in gold nanodots (diameter = 16 nm) was confirmed by comparing with devices having no gold nanoparticles, although the effects of interfacial traps may be also significant. The data retention time of the transistor memory is about 60 seconds, which needs to be further improved. It appears that this is the first demonstration of memory effects in an organic transistor caused by charge storage in metal nanodots in the gate dielectric. Therefore, the approach reported in this work offers a new direction to make low-cost organic transistor memories

Synthesis of silicon nanocrystal memories by sputter deposition

Aim of this work was, to investigate the preparation of Si NC memories by sputter deposition. The milestones are as follows: - Review of relevant literature. - Development of processes for an ultrathin tunnel-oxide and high quality sputtered SiO2 for use as control-oxide. - Evaluation of methods for the preparation of an oxygen-deficient silicon oxide inter-layer (the precursor of the Si NC layer). - Characterization of deposited films. - Establishment of techniques capable of probing the phase separation of SiOx and the formation of Si NC. - Establishment of annealing conditions compatible with the requirements of current CMOS technology based on experimental results and simulations of Si NC formation. - Preparation Si NC memory capacitors using the developed processes. - Characterization of these devices by suitable techniques. Demonstration of their memory functionality

Defect Induced Aging and Breakdown in High-k Dielectrics

abstract: High-k dielectrics have been employed in the metal-oxide semiconductor field effect transistors (MOSFETs) since 45 nm technology node. In this MOSFET industry, Moore’s law projects the feature size of MOSFET scales half within every 18 months. Such scaling down theory has not only led to the physical limit of manufacturing but also raised the reliability issues in MOSFETs. After the incorporation of HfO2 based high-k dielectrics, the stacked oxides based gate insulator is facing rather challenging reliability issues due to the vulnerable HfO2 layer, ultra-thin interfacial SiO2 layer, and even messy interface between SiO2 and HfO2. Bias temperature instabilities (BTI), hot channel electrons injections (HCI), stress-induced leakage current (SILC), and time dependent dielectric breakdown (TDDB) are the four most prominent reliability challenges impacting the lifetime of the chips under use. In order to fully understand the origins that could potentially challenge the reliability of the MOSFETs the defects induced aging and breakdown of the high-k dielectrics have been profoundly investigated here. BTI aging has been investigated to be related to charging effects from the bulk oxide traps and generations of Si-H bonds related interface traps. CVS and RVS induced dielectric breakdown studies have been performed and investigated. The breakdown process is regarded to be related to oxygen vacancies generations triggered by hot hole injections from anode. Post breakdown conduction study in the RRAM devices have shown irreversible characteristics of the dielectrics, although the resistance could be switched into high resistance state.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Ferroelectric field effect at ionically conducting oxide interfaces

Tesis de la Universidad Complutense de Madrid, Facultad de Ciencias Físicas, leída el 17-01-2019En este trabajo, realizamos un análisis de la interacción entre la ferroelectricidad, las paredes de dominio ferroeléctrico cargadas y el memristor en las dimensiones reducidas de una unión túnel. Para alcanzar este objetivo, crecemos bicapas de heteroestructuras epitaxiales de manganitas ferromagnéticas.The main findings of this dissertation are summarized here. We performed an analysis of the interplay between ferroelectricity, ferromagnetism, domain structure and memristive response inmagnetic tunnel junctions. In order to reach this objective, we grew epitaxial heterostructures combining ferromagnetic manganites.Fac. de Ciencias FísicasTRUEunpu