Fast computation of continued fractions

AbstractWe give an O(log n) algorithm to compute the nth convergent of a periodic continued fraction. The algorithm is based on matrix representation of continued fractions, due to Milne-Thomson. This approach also allows for the computation of first n convergents of a general continued fraction in O(log n) time using O(nlog n) processors

A sweep algorithm for massively parallel simulation of circuit-switched networks

A new massively parallel algorithm is presented for simulating large asymmetric circuit-switched networks, controlled by a randomized-routing policy that includes trunk-reservation. A single instruction multiple data (SIMD) implementation is described, and corresponding experiments on a 16384 processor MasPar parallel computer are reported. A multiple instruction multiple data (MIMD) implementation is also described, and corresponding experiments on an Intel IPSC/860 parallel computer, using 16 processors, are reported. By exploiting parallelism, our algorithm increases the possible execution rate of such complex simulations by as much as an order of magnitude

An improved algorithm for the p-center problem on interval graphs with unit lengths

2006-2007 > Academic research: refereed > Publication in refereed journalAccepted ManuscriptPublishe

Data broadcasting and reduction, prefix computation, and sorting on reduced hypercube (RH) parallel computers

The binary hypercube parallel computer has been very popular due to its rich interconnection structure and small average internode distance which allow the efficient embedding of frequently used topologies. Communication patterns of many parallel algorithms also match the hypercube topology. The hypercube has high VLSI complexity. however. due to the logarithmic increase in the number of connections to each node with the increase in the number of dimensions of the hypercube. The reduced hypercube (RH) interconnection network. which is obtained by a uniform reduction in the number of links for each hypercube node. yields lower-complexity interconnection networks when compared to hypercubes with the same number of nodes. It has been shown elsewhere that the RH interconnection network achieves performance comparable to that of the hypercube. at lower hardware cost. The reduced VLSI complexity of the RH also permits the construction of larger systems. thus. making the RH suitable for massively parallel processing. This thesis proposes algorithms for data broadcasting and reduction. prefix computation, and sorting on the RH parallel computer. All these operations are fundamental to many parallel algorithms. A worst case analysis of each algorithm is given and compared with equivalent- algorithms for the regular hypercube. It is shown that the proposed algorithms for the RH yield performance comparable to that for the regular hypercube

Size-Time Complexity of Boolean Networks for Prefix Computations

Coordinated Science Laboratory was formerly known as Control Systems LaboratoryNational Science Foundation / DCI-8602256 and ECS-84-1090