Miniature and Low-Power Wireless Sensor Node Platform: State of the Art and Current Trends

Wireless sensor node is an autonomous and compact device that has capability to monitor a variety of real-world phenomena. It is designed composed of sensing device, embedded processor, communication module, and power equipment. Wireless sensor node is part of wireless sensor network where hundred or thousand sensor node can be deployed. Over the past decade Wireless Sensor Networks (WSNs) have emerged as one of the computing platforms of note within the electronics community. In prediction, there will be more than 127 million wireless sensor nodes deployed worldwide by 2014. We have surveyed 100 currently available wireless sensor network node platforms have been developed and produced not only by the research institutions, the universities but also some companies in last ten years. In this paper, we present a review of 27 different wireless sensor node platforms. We review these devices under a number of different parameters, and we highlight the key advantages of each node platform according to dimension and power consumption. We also discuss the characteristics and trend of development and deployment a wireless sensor node technology

Visually-Prompted Language Model for Fine-Grained Scene Graph Generation in an Open World

Scene Graph Generation (SGG) aims to extract relationships in images for vision understanding. Although recent works have made steady progress on SGG, they still suffer long-tail distribution issues that tail-predicates are more costly to train and hard to distinguish due to a small amount of annotated data compared to frequent predicates. Existing re-balancing strategies try to handle it via prior rules but are still confined to pre-defined conditions, which are not scalable for various models and datasets. In this paper, we propose a Cross-modal prediCate boosting (CaCao) framework, where a visually-prompted language model is learned to generate diverse fine-grained predicates in a low-resource way. The proposed CaCao can be applied in a plug-and-play fashion and automatically strengthen existing SGG to tackle the long-tailed problem. Based on that, we further introduce a novel Entangled cross-modal prompt approach for open-world predicate scene graph generation (Epic), where models can generalize to unseen predicates in a zero-shot manner. Comprehensive experiments on three benchmark datasets show that CaCao consistently boosts the performance of multiple scene graph generation models in a model-agnostic way. Moreover, our Epic achieves competitive performance on open-world predicate prediction. The data and code for this paper are publicly available.Comment: Accepted by ICCV 202

Stream ciphers for secure display

In any situation where private, proprietary or highly confidential material is being dealt with, the need to consider aspects of data security has grown ever more important. It is usual to secure such data from its source, over networks and on to the intended recipient. However, data security considerations typically stop at the recipient's processor, leaving connections to a display transmitting raw data which is increasingly in a digital format and of value to an adversary. With a progression to wireless display technologies the prominence of this vulnerability is set to rise, making the implementation of 'secure display' increasingly desirable. Secure display takes aspects of data security right to the display panel itself, potentially minimising the cost, component count and thickness of the final product. Recent developments in display technologies should help make this integration possible. However, the processing of large quantities of time-sensitive data presents a significant challenge in such resource constrained environments. Efficient high- throughput decryption is a crucial aspect of the implementation of secure display and one for which the widely used and well understood block cipher may not be best suited. Stream ciphers present a promising alternative and a number of strong candidate algorithms potentially offer the hardware speed and efficiency required. In the past, similar stream ciphers have suffered from algorithmic vulnerabilities. Although these new-generation designs have done much to respond to this concern, the relatively short 80-bit key lengths of some proposed hardware candidates, when combined with ever-advancing computational power, leads to the thesis identifying exhaustive search of key space as a potential attack vector. To determine the value of protection afforded by such short key lengths a unique hardware key search engine for stream ciphers is developed that makes use of an appropriate data element to improve search efficiency. The simulations from this system indicate that the proposed key lengths may be insufficient for applications where data is of long-term or high value. It is suggested that for the concept of secure display to be accepted, a longer key length should be used

Assessing and characterizing the cognitive power of machine consciousness implementations

Proceeding of: AAAI 2009 Biologically Inspired Cognitive Architectures-II (BICA-2009). Technical Report FS-09-01. Washington, D.C. EE.UU, 5-7 Noviembre 2009.Many aspects can be taken into account in order to assess the power and potential of a cognitive architecture. In this paper we argue that ConsScale, a cognitive scale inspired on the development of consciousness, can be used to characterize and evaluate cognitive architectures from the point of view of the effective integration of their cognitive functionalities. Additionally, a graphical characterization of the cognitive power of artificial agents is proposed as a helpful tool for the analysis and comparison of Machine Consciousness implementations. This is illustrated with the application of the scale to a particular problem domain in the context of video game synthetic bots.This research has been supported by the Spanish Ministry of Education under CICYT grant TRA2007-67374-C02-02.Publicad

The design and implementation of PowerMill

In this paper we discuss the design and implemen-tation of the simulator PowerMill, a novel transistor level simulator for the simulation of current and power behavior in vlsi circuits. With a new transistor mod-eling technology and a versatile event driven simu-lation algorithm, PowerMill is capable of simulating detailed current behavior in modern deep-submicron cmos circuits, including sophisticated circuitries such as exclusive-or gates and sense-ampliers, with speed and capacity approaching conventional gate level sim-ulators. The high accuracy and speed have made it possible for designers to study and verify detailed cur-rent behavior of large functional blocks or even an en-tire chip with a reasonable amount of CPU resources, making it a de facto industry standard for power sim-ulation.