Analysis of Residue Probability Density Function and Comparator Offset Error in Pipelined ADCs

This paper presents a new approach to analyze the convergence of residue probability density function (pdf) in pipelined ADCs. Compared to the previous approaches, in the proposed approach, in addition to the analysis of residue pdfs for different input densities, the analysis of the sub-ADC comparator offsets impact on output pdf is possible. Using Fourier analysis, it will be shown that the residue density converges to uniformity. In the half-bit redundant structure, residue pdf concentrates in the center half of the stage full-scale range and 6 dB of extra resolution can be gained. Also, the share of each stage in this resolution improvement is investigated. Examining the sub-ADC threshold offsets impact on residue pdfs, it is observed that with respect to the impact on converter additional resolution, the final stages offset errors are more significant than the first stages offsets

Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters

In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and resolution requirements. This is due to the one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling. This work examines the traditional binary capacitive SAR ADC time and statistical information and proposes new structures that optimize ADC performance. The Ternary SAR (TSAR) uses the quantizer delay information to enhance accuracy, speed and power consumption of the overall SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR (EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quanitzer structure for a Ternary MCS DAC. Residue Shaping is demonstrated in SAR and pipeline configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multi-level redundancy. The feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR into separate binary and ternary sub-ADC structures for speed and power benefits with an inter-stage encoding that not only maintains residue shaping across the binary SAR, but allows for nearly optimally minimal energy consumption for capacitive ternary DACs. Finally, the ternary SAR ideas are applied to R2R DACs to reduce power consumption. These ideas are tested both in simulation and with prototype results

Redundant analog to digital conversion architectures in CMOS technology

The operation of modern electronic devices in different fields as communications, signal processing, and sensor interface is critically affected with robust, high performance and scalable Analog-to-Digital Converter (ADCs), that can be considered as one of the main blocks in many systems, since they are mandatory to make the link between the analog outside world and the evermore-ubiquitous digital computer world. The design of these ADCs come distinct tradeoffs between speed, power, resolution, and die area embodied within many data conversion architectural variations. The flash ADC structure are often the base structure for high-speed operation and simple architecture analog-to-digital converters (ADCs). As the input signal is applied to (

Redundant analog to digital conversion architectures in CMOS technology

The operation of modern electronic devices in different fields as communications, signal processing, and sensor interface is critically affected with robust, high performance and scalable Analog-to-Digital Converter (ADCs), that can be considered as one of the main blocks in many systems, since they are mandatory to make the link between the analog outside world and the evermore-ubiquitous digital computer world. The design of these ADCs come distinct tradeoffs between speed, power, resolution, and die area embodied within many data conversion architectural variations. The flash ADC structure are often the base structure for high-speed operation and simple architecture analog-to-digital converters (ADCs). As the input signal is applied to (

Mismatch-Immune Successive-Approximation Techniques for Nanometer CMOS ADCs

During the past decade, SAR ADCs have enjoyed increasing prominence due to their inherently scaling-friendly architecture. Several recent SAR ADC innovations focus on decreasing power consumption, mitigating thermal noise, and improving bandwidth, however most of those that use non-hybrid architectures are limited to moderate (8-10 bit) resolu- tion. Assuming an almost rail-to-rail dynamic range, comparator noise and DAC element mismatch constraints are critical but not insurmountable at 10 bits of resolution or less in sub-100nm processes. On the other hand, analysis shows that for medium-resolution ADCs (11-15 bits, depending on the LSB voltage of the converter), the mismatch sizing constraint still dominates unit capacitor sizing over the kT/C sampling noise constraint, and can only be mitigated by drawing increasingly larger capacitors. The focus of this work is to extend the scaling benefits of the SAR architecture to medium and higher ADC resolutions through mitigating and ultimately harnessing DAC element mismatch. This goal is achieved via a novel, completely reconfigurable capacitor DAC that allows the rearranging of capacitors to different trial groupings in the SAR cycle so that mismatch can be canceled. The DAC is implemented in a 12-bit SAR ADC in 65nm CMOS, and a nearly 2-bit improvement in linearity is demonstrated with a simple reconfiguration algorithm.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138630/1/ncolins_1.pd

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS

With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington,MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100kSps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich,RI

Ultra Wideband Communications: from Analog to Digital

Ultrabreitband-Signale (Ultra Wideband [UWB]) können einen signifikanten Nutzen im Bereich drahtloser Kommunikationssysteme haben. Es sind jedoch noch einige Probleme offen, die durch Systemdesigner und Wissenschaftler gelöst werden müssen. Ein Funknetzsystem mit einer derart großen Bandbreite ist normalerweise auch durch eine große Anzahl an Mehrwegekomponenten mit jeweils verschiedenen Pfadamplituden gekennzeichnet. Daher ist es schwierig, die zeitlich verteilte Energie effektiv zu erfassen. Außerdem ist in vielen Fällen der naheliegende Ansatz, ein kohärenter Empfänger im Sinne eines signalangepassten Filters oder eines Korrelators, nicht unbedingt die beste Wahl. In der vorliegenden Arbeit wird dabei auf die bestehende Problematik und weitere Lösungsmöglichkeiten eingegangen. Im ersten Abschnitt geht es um „Impulse Radio UWB”-Systeme mit niedriger Datenrate. Bei diesen Systemen kommt ein inkohärenter Empfänger zum Einsatz. Inkohärente Signaldetektion stellt insofern einen vielversprechenden Ansatz dar, als das damit aufwandsgünstige und robuste Implementierungen möglich sind. Dies trifft vor allem in Anwendungsfällen wie den von drahtlosen Sensornetzen zu, wo preiswerte Geräte mit langer Batterielaufzeit nötigsind. Dies verringert den für die Kanalschätzung und die Synchronisation nötigen Aufwand, was jedoch auf Kosten der Leistungseffizienz geht und eine erhöhte Störempfindlichkeit gegenüber Interferenz (z.B. Interferenz durch mehrere Nutzer oder schmalbandige Interferenz) zur Folge hat. Um die Bitfehlerrate der oben genannten Verfahren zu bestimmen, wurde zunächst ein inkohärenter Combining-Verlust spezifiziert, welcher auftritt im Gegensatz zu kohärenter Detektion mit Maximum Ratio Multipath Combining. Dieser Verlust hängt von dem Produkt aus der Länge des Integrationsfensters und der Signalbandbreite ab. Um den Verlust durch inkohärentes Combining zu reduzieren und somit die Leistungseffizienz des Empfängers zu steigern, werden verbesserte Combining-Methoden für Mehrwegeempfang vorgeschlagen. Ein analoger Empfänger, bei dem der Hauptteil des Mehrwege-Combinings durch einen „Integrate and Dump”-Filter implementiert ist, wird für UWB-Systeme mit Zeit-Hopping gezeigt. Dabei wurde die Einsatzmöglichkeit von dünn besetzten Codes in solchen System diskutiert und bewertet. Des Weiteren wird eine Regel für die Code-Auswahl vorgestellt, welche die Stabilität des Systems gegen Mehrnutzer-Störungen sicherstellt und gleichzeitig den Verlust durch inkohärentes Combining verringert. Danach liegt der Fokus auf digitalen Lösungen bei inkohärenter Demodulation. Im Vergleich zum Analogempfänger besitzt ein Digitalempfänger einen Analog-Digital-Wandler im Zeitbereich gefolgt von einem digitalen Optimalfilter. Der digitale Optimalfilter dekodiert den Mehrfachzugriffscode kohärent und beschränkt das inkohärente Combining auf die empfangenen Mehrwegekomponenten im Digitalbereich. Es kommt ein schneller Analog-Digital-Wandler mit geringer Auflösung zum Einsatz, um einen vertretbaren Energieverbrauch zu gewährleisten. Diese Digitaltechnik macht den Einsatz langer Analogverzögerungen bei differentieller Demodulation unnötig und ermöglicht viele Arten der digitalen Signalverarbeitung. Im Vergleich zur Analogtechnik reduziert sie nicht nur den inkohärenten Combining-Verlust, sonder zeigt auch eine stärkere Resistenz gegenüber Störungen. Dabei werden die Auswirkungen der Auflösung und der Abtastrate der Analog-Digital-Umsetzung analysiert. Die Resultate zeigen, dass die verminderte Effizienz solcher Analog-Digital-Wandler gering ausfällt. Weiterhin zeigt sich, dass im Falle starker Mehrnutzerinterferenz sogar eine Verbesserung der Ergebnisse zu beobachten ist. Die vorgeschlagenen Design-Regeln spezifizieren die Anwendung der Analog-Digital-Wandler und die Auswahl der Systemparameter in Abhängigkeit der verwendeten Mehrfachzugriffscodes und der Modulationsart. Wir zeigen, wie unter Anwendung erweiterter Modulationsverfahren die Leistungseffizienz verbessert werden kann und schlagen ein Verfahren zur Unterdrückung schmalbandiger Störer vor, welches auf Soft Limiting aufbaut. Durch die Untersuchungen und Ergebnissen zeigt sich, dass inkohärente Empfänger in UWB-Kommunikationssystemen mit niedriger Datenrate ein großes Potential aufweisen. Außerdem wird die Auswahl der benutzbaren Bandbreite untersucht, um einen Kompromiss zwischen inkohärentem Combining-Verlust und Stabilität gegenüber langsamen Schwund zu erreichen. Dadurch wurde ein neues Konzept für UWB-Systeme erarbeitet: wahlweise kohärente oder inkohärente Empfänger, welche als UWB-Systeme Frequenz-Hopping nutzen. Der wesentliche Vorteil hiervon liegt darin, dass die Bandbreite im Basisband sich deutlich verringert. Mithin ermöglicht dies einfach zu realisierende digitale Signalverarbeitungstechnik mit kostengünstigen Analog-Digital-Wandlern. Dies stellt eine neue Epoche in der Forschung im Bereich drahtloser Sensorfunknetze dar. Der Schwerpunkt des zweiten Abschnitts stellt adaptiven Signalverarbeitung für hohe Datenraten mit „Direct Sequence”-UWB-Systemen in den Vordergrund. In solchen Systemen entstehen, wegen der großen Anzahl der empfangenen Mehrwegekomponenten, starke Inter- bzw. Intrasymbolinterferenzen. Außerdem kann die Funktionalität des Systems durch Mehrnutzerinterferenz und Schmalbandstörungen deutlich beeinflusst werden. Um sie zu eliminieren, wird die „Widely Linear”-Rangreduzierung benutzt. Dabei verbessert die Rangreduzierungsmethode das Konvergenzverhalten, besonders wenn der gegebene Vektor eine sehr große Anzahl an Abtastwerten beinhaltet (in Folge hoher einer Abtastrate). Zusätzlich kann das System durch die Anwendung der R-linearen Verarbeitung die Statistik zweiter Ordnung des nicht-zirkularen Signals vollständig ausnutzen, was sich in verbesserten Schätzergebnissen widerspiegelt. Allgemeine kann die Methode der „Widely Linear”-Rangreduzierung auch in andern Bereichen angewendet werden, z.B. in „Direct Sequence”-Codemultiplexverfahren (DS-CDMA), im MIMO-Bereich, im Global System for Mobile Communications (GSM) und beim Beamforming.The aim of this thesis is to investigate key issues encountered in the design of transmission schemes and receiving techniques for Ultra Wideband (UWB) communication systems. Based on different data rate applications, this work is divided into two parts, where energy efficient and robust physical layer solutions are proposed, respectively. Due to a huge bandwidth of UWB signals, a considerable amount of multipath arrivals with various path gains is resolvable at the receiver. For low data rate impulse radio UWB systems, suboptimal non-coherent detection is a simple way to effectively capture the multipath energy. Feasible techniques that increase the power efficiency and the interference robustness of non-coherent detection need to be investigated. For high data rate direct sequence UWB systems, a large number of multipath arrivals results in severe inter-/intra-symbol interference. Additionally, the system performance may also be deteriorated by multi-user interference and narrowband interference. It is necessary to develop advanced signal processing techniques at the receiver to suppress these interferences. Part I of this thesis deals with the co-design of signaling schemes and receiver architectures in low data rate impulse radio UWB systems based on non-coherent detection.● We analyze the bit error rate performance of non-coherent detection and characterize a non-coherent combining loss, i.e., a performance penalty with respect to coherent detection with maximum ratio multipath combining. The thorough analysis of this loss is very helpful for the design of transmission schemes and receive techniques innon-coherent UWB communication systems.● We propose to use optical orthogonal codes in a time hopping impulse radio UWB system based on an analog non-coherent receiver. The “analog” means that the major part of the multipath combining is implemented by an integrate and dump filter. The introduced semi-analytical method can help us to easily select the time hopping codes to ensure the robustness against the multi-user interference and meanwhile to alleviate the non-coherent combining loss.● The main contribution of Part I is the proposal of applying fully digital solutions in non-coherent detection. The proposed digital non-coherent receiver is based on a time domain analog-to-digital converter, which has a high speed but a very low resolution to maintain a reasonable power consumption. Compared to its analog counterpart, itnot only significantly reduces the non-coherent combining loss but also offers a higher interference robustness. In particular, the one-bit receiver can effectively suppress strong multi-user interference and is thus advantageous in separating simultaneously operating piconets.The fully digital solutions overcome the difficulty of implementing long analog delay lines and make differential UWB detection possible. They also facilitate the development of various digital signal processing techniques such as multi-user detection and non-coherent multipath combining methods as well as the use of advanced modulationschemes (e.g., M-ary Walsh modulation).● Furthermore, we present a novel impulse radio UWB system based on frequency hopping, where both coherent and non-coherent receivers can be adopted. The key advantage is that the baseband bandwidth can be considerably reduced (e.g., lower than 500 MHz), which enables low-complexity implementation of the fully digital solutions. It opens up various research activities in the application field of wireless sensor networks. Part II of this thesis proposes adaptive widely linear reduced-rank techniques to suppress interferences for high data rate direct sequence UWB systems, where second-order non-circular signals are used. The reduced-rank techniques are designed to improve the convergence performance and the interference robustness especially when the received vector contains a large number of samples (due to a high sampling rate in UWB systems). The widely linear processing takes full advantage of the second-order statistics of the non-circular signals and enhances the estimation performance. The generic widely linear reduced-rank concept also has a great potential in the applications of other systems such as Direct Sequence Code Division Multiple Access (DS-CDMA), Multiple Input Multiple Output (MIMO) system, and Global System for Mobile Communications (GSM), or in other areas such as beamforming

Realization Limits of Impulse-Radio UWB Indoor Localization Systems

In this work, the realization limits of an impulse-based Ultra-Wideband (UWB) localization system for indoor applications have been thoroughly investigated and verified by measurements. The analysis spans from the position calculation algorithms, through hardware realization and modeling, up to the localization experiments conducted in realistic scenarios. The main focus was put on identification and characterization of limiting factors as well as developing methods to overcome them

Nonlinear models and algorithms for RF systems digital calibration

Focusing on the receiving side of a communication system, the current trend in pushing the digital domain ever more closer to the antenna sets heavy constraints on the accuracy and linearity of the analog front-end and the conversion devices. Moreover, mixed-signal implementations of Systems-on-Chip using nanoscale CMOS processes result in an overall poorer analog performance and a reduced yield. To cope with the impairments of the low performance analog section in this "dirty RF" scenario, two solutions exist: designing more complex analog processing architectures or to identify the errors and correct them in the digital domain using DSP algorithms. In the latter, constraints in the analog circuits' precision can be offloaded to a digital signal processor. This thesis aims at the development of a methodology for the analysis, the modeling and the compensation of the analog impairments arising in different stages of a receiving chain using digital calibration techniques. Both single and multiple channel architectures are addressed exploiting the capability of the calibration algorithm to homogenize all the channels' responses of a multi-channel system in addition to the compensation of nonlinearities in each response. The systems targeted for the application of digital post compensation are a pipeline ADC, a digital-IF sub-sampling receiver and a 4-channel TI-ADC. The research focuses on post distortion methods using nonlinear dynamic models to approximate the post-inverse of the nonlinear system and to correct the distortions arising from static and dynamic errors. Volterra model is used due to its general approximation capabilities for the compensation of nonlinear systems with memory. Digital calibration is applied to a Sample and Hold and to a pipeline ADC simulated in the 45nm process, demonstrating high linearity improvement even with incomplete settling errors enabling the use of faster clock speeds. An extended model based on the baseband Volterra series is proposed and applied to the compensation of a digital-IF sub-sampling receiver. This architecture envisages frequency selectivity carried out at IF by an active band-pass CMOS filter causing in-band and out-of-band nonlinear distortions. The improved performance of the proposed model is demonstrated with circuital simulations of a 10th-order band pass filter, realized using a five-stage Gm-C Biquad cascade, and validated using out-of-sample sinusoidal and QAM signals. The same technique is extended to an array receiver with mismatched channels' responses showing that digital calibration can compensate the loss of directivity and enhance the overall system SFDR. An iterative backward pruning is applied to the Volterra models showing that complexity can be reduced without impacting linearity, obtaining state-of-the-art accuracy/complexity performance. Calibration of Time-Interleaved ADCs, widely used in RF-to-digital wideband receivers, is carried out developing ad hoc models because the steep discontinuities generated by the imperfect canceling of aliasing would require a huge number of terms in a polynomial approximation. A closed-form solution is derived for a 4-channel TI-ADC affected by gain errors and timing skews solving the perfect reconstruction equations. A background calibration technique is presented based on cyclo-stationary filter banks architecture. Convergence speed and accuracy of the recursive algorithm are discussed and complexity reduction techniques are applied