Plug & Test at System Level via Testable TLM Primitives

With the evolution of Electronic System Level (ESL) design methodologies, we are experiencing an extensive use of Transaction-Level Modeling (TLM). TLM is a high-level approach to modeling digital systems where details of the communication among modules are separated from the those of the implementation of functional units. This paper represents a first step toward the automatic insertion of testing capabilities at the transaction level by definition of testable TLM primitives. The use of testable TLM primitives should help designers to easily get testable transaction level descriptions implementing what we call a "Plug & Test" design methodology. The proposed approach is intended to work both with hardware and software implementations. In particular, in this paper we will focus on the design of a testable FIFO communication channel to show how designers are given the freedom of trading-off complexity, testability levels, and cos

IEEE Standard 1500 Compliance Verification for Embedded Cores

Core-based design and reuse are the two key elements for an efficient system-on-chip (SoC) development. Unfortunately, they also introduce new challenges in SoC testing, such as core test reuse and the need of a common test infrastructure working with cores originating from different vendors. The IEEE 1500 Standard for Embedded Core Testing addresses these issues by proposing a flexible hardware test wrapper architecture for embedded cores, together with a core test language (CTL) used to describe the implemented wrapper functionalities. Several intellectual property providers have already announced IEEE Standard 1500 compliance in both existing and future design blocks. In this paper, we address the problem of guaranteeing the compliance of a wrapper architecture and its CTL description to the IEEE Standard 1500. This step is mandatory to fully trust the wrapper functionalities in applying the test sequences to the core. We present a systematic methodology to build a verification framework for IEEE Standard 1500 compliant cores, allowing core providers and/or integrators to verify the compliance of their products (sold or purchased) to the standar

Evaluasi dan Perbaikan Kualitas Desain Diagram Kelas

Dalam proses pengembangan dan pemeliharaan proyek perangkat lunak, kualitas merupakan salah satu hal penting yang menjadi penentu keberhasilan perangkat lunak.Kesalahan yang tidak ditemukan pada awal pengembangan akan membutuhkan sumber daya, biaya, dan waktu perbaikan yang lebih tinggi. Salah satu tahapan yang dilakukan saat proses pengembangan perangkat lunak adalah pemodelan data. Pada perangkat lunak yang berorientasi objek, data biasanya dimodelkan dalam bentuk diagram kelas. Kualitas pada diagram kelas sangat tergantung pada pengetahuan dari perancang. Oleh karena itu, berbagai metrik telah dikembangkan untuk menilai kualitas desain dari berbagai aspek. Pada paper ini, Penulis mengusulkan sebuah pendekatan dan model untuk mengevaluasi, mendeteksi, dan memperbaiki desain kelas diagram, sehingga sesuai dengan kriteria kualitas yang diharapkan

Optimal Approach to Compute Metrics for Structural and Behavioural Diagrams of UML using Program Slicing Techniques

We have purposed an optimal approach for computing the various complexity metrics for different UML diagrams by using the program slicing techniques. Firstly, we draw the UML diagrams in Argo UML software then XML file is generated then by using the SD Metrics Tool different parameters were calculated automatically. The dependency graph is drawn then the slicing criteria is adopted by using our purposed algorithm then complexity metrics were calculated. After applying the program slicing techniques the complexity of any diagram will be decreased and will easier for testability, maintainability, readability, and modularity

Goal sketching with activity diagrams

Goal orientation is acknowledged as an important paradigm in requirements engineering. The structure of a goal-responsibility model provides opportunities for appraising the intention of a development. Creating a suitable model under agile constraints (time, incompleteness and catching up after an initial burst of creativity) can be challenging. Here we propose a marriage of UML activity diagrams with goal sketching in order to facilitate the production of goal responsibility models under these constraints

Testability Assessment Model for Object Oriented Software based on Internal and External Quality Factors

Software testability is coming out to be most frequent talked about subject then the underrated and unpopular quality factor it used to be in past few years. The correct and timely assessment of testability can lead to improvisation of software testing process. Though many researchers and quality controllers have proved its importance, but still the research has not gained much momentum in emphasizing the need of making testability analysis necessary during all software development phases. In this paper we review and analyse the factors affecting testability estimation of object oriented software systems during design and analysis phase of development life cycle. These factors are then linked together in the form of new assessment model for object oriented software testability. The proposed model will be evaluated using analytical hierarchical process (AHP)