VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Copper to copper bonding by nano interfaces for fine pitch interconnections and thermal applications

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law at IC level and system miniaturization with System-On-Package (SOP) paradigm at system level, have resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. However, system miniaturization poses several electrical and thermal challenges that demand innovative solutions including advanced materials, bonding and assembly techniques. Heterogeneous material and device integration for thermal structures and IC assembly are limited by the bonding technology and the electrical and thermal impedance of the bonding interfaces. Solder - based bonding technology that is prevalent today is a major limitation to future systems. The trend towards miniaturized systems is expected to drive downscaling of IC I/O pad pitches from 40µm to 1- 5µm in future. Solder technology imposes several pitch, processability and cost restrictions at such fine pitches. Furthermore, according to International Technology Roadmap for Semiconductors (ITRS-2006), the supply current in high performance microprocessors is expected to increase to 220 A by 2012. At such supply current, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer sized technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Similarly, thermal power dissipation is growing to unprecedented high with a projected power of 198 W by 2008 (ITRS 2006). Present thermal interfaces are not adequate for such high heat dissipation. Recently, copper based thin film bonding has become a promising approach to address the abovementioned challenges. However, copper-copper direct bonding without using solders has not been studied thoroughly. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. Hence, there is a need to develop a novel low temperature copper to copper bonding process. In the present study, nanomaterials - based copper-to-copper bonding is explored and developed as an alternative to solder-based bonding. To demonstrate fine pitch bonding, the patterning of these nanoparticles is crucial. Therefore, two novel self-patterning techniques based on: 1.) Selective wetting and 2.) Selective nanoparticle deposition, are developed to address this challenge. Nanoparticle active layer facilitates diffusion and, thus, a reliable bond can be achieved using less thermal budget. Quantitative characterization of the bonding revealed good metallurgical bonding with very high bond strength. This has been confirmed by several morphological and structural characterizations. A 30-micron pitch IC assembly test vehicle is used to demonstrate fine pitch patternability and bonding. In conclusion, novel nanoparticle synthesis and patterning techniques were developed and demonstrated for low-impedance and low-cost electrical and thermal interfaces.M.S.Committee Chair: Rao R. Tummala; Committee Member: C. P. Wong; Committee Member: P. M. Ra

NASA SBIR abstracts of 1991 phase 1 projects

The objectives of 301 projects placed under contract by the Small Business Innovation Research (SBIR) program of the National Aeronautics and Space Administration (NASA) are described. These projects were selected competitively from among proposals submitted to NASA in response to the 1991 SBIR Program Solicitation. The basic document consists of edited, non-proprietary abstracts of the winning proposals submitted by small businesses. The abstracts are presented under the 15 technical topics within which Phase 1 proposals were solicited. Each project was assigned a sequential identifying number from 001 to 301, in order of its appearance in the body of the report. Appendixes to provide additional information about the SBIR program and permit cross-reference of the 1991 Phase 1 projects by company name, location by state, principal investigator, NASA Field Center responsible for management of each project, and NASA contract number are included

Many-core and heterogeneous architectures: programming models and compilation toolchains

1noL'abstract è presente nell'allegato / the abstract is in the attachmentopen677. INGEGNERIA INFORMATInopartially_openembargoed_20211002Barchi, Francesc

Workshop proceedings: Information Systems for Space Astrophysics in the 21st Century, volume 1

The Astrophysical Information Systems Workshop was one of the three Integrated Technology Planning workshops. Its objectives were to develop an understanding of future mission requirements for information systems, the potential role of technology in meeting these requirements, and the areas in which NASA investment might have the greatest impact. Workshop participants were briefed on the astrophysical mission set with an emphasis on those missions that drive information systems technology, the existing NASA space-science operations infrastructure, and the ongoing and planned NASA information systems technology programs. Program plans and recommendations were prepared in five technical areas: Mission Planning and Operations; Space-Borne Data Processing; Space-to-Earth Communications; Science Data Systems; and Data Analysis, Integration, and Visualization

Fast convolutional neural networks on FPGAs with hls4ml

We introduce an automated tool for deploying ultra low-latency, low-power deep neural networks with convolutional layers on FPGAs. By extending the hls4ml library, we demonstrate an inference latency of $5\,\mu$s using convolutional architectures, targeting microsecond latency applications like those at the CERN Large Hadron Collider. Considering benchmark models trained on the Street View House Numbers Dataset, we demonstrate various methods for model compression in order to fit the computational constraints of a typical FPGA device used in trigger and data acquisition systems of particle detectors. In particular, we discuss pruning and quantization-aware training, and demonstrate how resource utilization can be significantly reduced with little to no loss in model accuracy. We show that the FPGA critical resource consumption can be reduced by 97% with zero loss in model accuracy, and by 99% when tolerating a 6% accuracy degradation.Comment: 18 pages, 18 figures, 4 table

Vidutinių dažnių 5G belaidžių tinklų galios stiprintuvų tyrimas

This dissertation addresses the problems of ensuring efficient radio fre-quency transmission for 5G wireless networks. Taking into account, that the next generation 5G wireless network structure will be heterogeneous, the device density and their mobility will increase and massive MIMO connectivity capability will be widespread, the main investigated problem is formulated – increasing the efficiency of portable mid-band 5G wireless network CMOS power amplifier with impedance matching networks. The dissertation consists of four parts including the introduction, 3 chapters, conclusions, references and 3 annexes. The investigated problem, importance and purpose of the thesis, the ob-ject of the research methodology, as well as the scientific novelty are de-fined in the introduction. Practical significance of the obtained results, defended state-ments and the structure of the dissertation are also included. The first chapter presents an extensive literature analysis. Latest ad-vances in the structure of the modern wireless network and the importance of the power amplifier in the radio frequency transmission chain are de-scribed in detail. The latter is followed by different power amplifier archi-tectures, parameters and their improvement techniques. Reported imped-ance matching network design methods are also discussed. Chapter 1 is concluded distinguishing the possible research vectors and defining the problems raised in this dissertation. The second chapter is focused around improving the accuracy of de-signing lumped impedance matching network. The proposed methodology of estimating lumped inductor and capacitor parasitic parameters is dis-cussed in detail provi-ding complete mathematical expressions, including a summary and conclusions. The third chapter presents simulation results for the designed radio fre-quency power amplifiers. Two variations of Doherty power amplifier archi-tectures are presented in the second part, covering the full step-by-step de-sign and simulation process. The latter chapter is concluded by comparing simulation and measurement results for all designed radio frequency power amplifiers. General conclusions are followed by an extensive list of references and a list of 5 publications by the author on the topic of the dissertation. 5 papers, focusing on the subject of the discussed dissertation, have been published: three papers are included in the Clarivate Analytics Web of Sci-ence database with a citation index, one paper is included in Clarivate Ana-lytics Web of Science database Conference Proceedings, and one paper has been published in unreferred international conference preceedings. The au-thor has also made 9 presentations at 9 scientific conferences at a national and international level.Dissertatio

Ultra thin ultrafine-pitch chip-package interconnections for embedded chip last approach

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.M.S.Committee Chair: Prof. Rao R Tummala; Committee Member: Dr. Jack Moon; Committee Member: Dr. P M Ra

Low-Impact Profiling of Streaming, Heterogeneous Applications

Computer engineers are continually faced with the task of translating improvements in fabrication process technology: i.e., Moore\u27s Law) into architectures that allow computer scientists to accelerate application performance. As feature-size continues to shrink, architects of commodity processors are designing increasingly more cores on a chip. While additional cores can operate independently with some tasks: e.g. the OS and user tasks), many applications see little to no improvement from adding more processor cores alone. For many applications, heterogeneous systems offer a path toward higher performance. Significant performance and power gains have been realized by combining specialized processors: e.g., Field-Programmable Gate Arrays, Graphics Processing Units) with general purpose multi-core processors. Heterogeneous applications need to be programmed differently than traditional software. One approach, stream processing, fits these systems particularly well because of the segmented memories and explicit expression of parallelism. Unfortunately, debugging and performance tools that support streaming, heterogeneous applications do not exist. This dissertation presents TimeTrial, a performance measurement system that enables performance optimization of streaming applications by profiling the application deployed on a heterogeneous system. TimeTrial performs low-impact measurements by dedicating computing resources to monitoring and by aggressively compressing performance traces into statistical summaries guided by user specification of the performance queries of interest