Layout level design for testability strategy applied to a CMOS cell library

The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce their appearance probability. The main purpose has been to apply that set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cell

Testability enhancement of a basic set of CMOS cells

Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect). Consequentially, layout level design for testability (LLDFT) rules have been developed, which prevent the faults, or at least reduce the chance of their appearing. The main purpose of this work is to apply a practical set of LLDFT rules to the library cells designed by the Centre Nacional de Microelectrònica (CNM) and obtain a highly testable cell library. The main results of the application of the LLDFT rules (area overheads and performance degradation) are summarized and the results are significant since IC design is highly repetitive; a small effort to improve cell layout can bring about great improvement in design

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Displacement damage effects due to neutron and proton irradiations on CMOS image sensors manufactured in deep submicron technology

Displacement damage effects due to proton and neutron irradiations of CMOS image sensors dedicated to imaging are presented through the analysis of the dark current behavior in pixel arrays and isolated photodiodes. The mean dark current increase and the dark current nonuniformity are investigated. Dark current histogram observations are compared to damage energy distributions based on GEANT 4 calculations. We also discuss, through annealing analysis, which defects could be responsible for the dark current in CMOS image sensors

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Influence of parasitic capacitance variations on 65 nm and 32 nm predictive technology model SRAM core-cells

The continuous improving of CMOS technology allows the realization of digital circuits and in particular static random access memories that, compared with previous technologies, contain an impressive number of transistors. The use of new production processes introduces a set of parasitic effects that gain more and more importance with the scaling down of the technology. In particular, even small variations of parasitic capacitances in CMOS devices are expected to become an additional source of faulty behaviors in future technologies. This paper analyzes and compares the effect of parasitic capacitance variations in a SRAM memory circuit realized with 65 nm and 32 nm predictive technology model

Analysis and Optimization of Noise Response for Low-Noise CMOS Image Sensors

CMOS image sensors are nowadays widely used in imaging applications and particularly in low light flux applications. This is really possible thanks to a reduction of noise obtained, among others, by the use of pinned photodiode associated with a Correlated Double Sampling readout. It reveals new noise sources which become the major contributors. This paper presents noise measurements on low-noise CMOS image sensor. Image sensor noise is analyzed and optimization is done in order to reach an input referred noise of 1 electron rms by column gain amplifier insertion and dark current noise optimization. Pixel array noise histograms are analyzed to determine noise impact of dark current and column gain amplifier insertion. Transfer noise impact, due to the use of pinned photodiode (4T photodiode), is also measured and analyzed by a specific readout sequence

Radiation Effects in CMOS Isolation Oxides: Differences and Similarities With Thermal Oxides

Radiation effects in thick isolation oxides of modern CMOS technologies are investigated using dedicated test structures designed using two commercial foundries. Shallow Trench Isolation and Pre-Metal Dielectric are studied using electrical measurements performed after X-ray irradiations and isochronal annealing cycles. This paper shows that trapping properties of such isolation oxides can strongly differ from those of traditional thermal oxides usually used to process the gate oxide of Metal Oxide Semiconductor Field Effect Transistors. Buildup and annealing of both radiation-induced oxide-trap charge and radiation-induced interface traps are discussed as a function of the oxide type, foundry and bias condition during irradiation. Radiation-induced interface traps in such isolation oxides are shown to anneal below 100°C contrary to what is usually observed in thermal oxides. Implications for design hardening and radiation tests of CMOS Integrated Circuits are discussed

Analysis of total dose-induced dark current in CMOS image sensors from interface state and trapped charge density measurements

The origin of total ionizing dose induced dark current in CMOS image sensors is investigated by comparing dark current measurements to interface state density and trapped charge density measurements. Two types of photodiode and several thick-oxide-FETs were manufactured using a 0.18-µm CMOS image sensor process and exposed to 10-keV X-ray from 3 krad to 1 Mrad. It is shown that the radiation induced trapped charge extends the space charge region at the oxide interface, leading to an enhancement of interface state SRH generation current. Isochronal annealing tests show that STI interface states anneal out at temperature lower than 100°C whereas about a third of the trapped charge remains after 30 min at 300°C