Circuit topology and synthesis flow co-design for the development of computational ReRAM

© 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Emerging memory technologies will play a decisive role in the quest for more energy-efficient computing systems. Computational ReRAM structures based on resistive switching devices (memristors) have been explored for in-memory computations using the resistance of ReRAM cells for storage and for logic I/O representation. Such approach presents three major challenges: the support for a memristor-oriented logic style, the ad-hoc design of memory array driving circuitry for memory and logic operations, and the development of dedicated synthesis tools to instruct the multi-level operations required for the execution of an arbitrary logic function in memory. This work contributes towards the development of an automated design flow for ReRAM-based computational memories, highlighting some important HW-SW co-design considerations. We briefly present a case study concerning a synthesis flow for a nonstateful logic style and the co-design of the underlying 1T1R crossbar array driving circuit. The prototype of the synthesis flow is based on the ABC tool and the Z3 solver. It executes fast owing to the level-by-level mapping of logic gates. Moreover, it delivers a mapping that minimizes the logic function latency through parallel logic operations, while also using the less possible ReRAM cells.Supported by Synopsys, Chile, by the Chilean grants FONDECYT Regular 1221747 and ANID-Basal FB0008, and by the Spanish MCIN/AEI/10.13039/501100011033 grant PID2019-103869RB-C33Peer ReviewedPostprint (author's final draft

Monatomic phase change memory

Phase change memory has been developed into a mature technology capable of storing information in a fast and non-volatile way, with potential for neuromorphic computing applications. However, its future impact in electronics depends crucially on how the materials at the core of this technology adapt to the requirements arising from continued scaling towards higher device densities. A common strategy to finetune the properties of phase change memory materials, reaching reasonable thermal stability in optical data storage, relies on mixing precise amounts of different dopants, resulting often in quaternary or even more complicated compounds. Here we show how the simplest material imaginable, a single element (in this case, antimony), can become a valid alternative when confined in extremely small volumes. This compositional simplification eliminates problems related to unwanted deviations from the optimized stoichiometry in the switching volume, which become increasingly pressing when devices are aggressively miniaturized. Removing compositional optimization issues may allow one to capitalize on nanosize effects in information storage

X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories

Silicon-based Static Random Access Memories (SRAM) and digital Boolean logic have been the workhorse of the state-of-art computing platforms. Despite tremendous strides in scaling the ubiquitous metal-oxide-semiconductor transistor, the underlying \textit{von-Neumann} computing architecture has remained unchanged. The limited throughput and energy-efficiency of the state-of-art computing systems, to a large extent, results from the well-known \textit{von-Neumann bottleneck}. The energy and throughput inefficiency of the von-Neumann machines have been accentuated in recent times due to the present emphasis on data-intensive applications like artificial intelligence, machine learning \textit{etc}. A possible approach towards mitigating the overhead associated with the von-Neumann bottleneck is to enable \textit{in-memory} Boolean computations. In this manuscript, we present an augmented version of the conventional SRAM bit-cells, called \textit{the X-SRAM}, with the ability to perform in-memory, vector Boolean computations, in addition to the usual memory storage operations. We propose at least six different schemes for enabling in-memory vector computations including NAND, NOR, IMP (implication), XOR logic gates with respect to different bit-cell topologies $-$ the 8T cell and the 8$^+$T Differential cell. In addition, we also present a novel \textit{`read-compute-store'} scheme, wherein the computed Boolean function can be directly stored in the memory without the need of latching the data and carrying out a subsequent write operation. The feasibility of the proposed schemes has been verified using predictive transistor models and Monte-Carlo variation analysis.Comment: This article has been accepted in a future issue of IEEE Transactions on Circuits and Systems-I: Regular Paper

Minimizing the programming power of phase change memory by using graphene nanoribbon edge-contact

Nonvolatile phase change random access memory (PCRAM) is regarded as one of promising candidates for emerging mass storage in the era of Big Data. However, relatively high programming energy hurdles the further reduction of power consumption in PCRAM. Utilizing narrow edge-contact of graphene can effectively reduce the active volume of phase change material in each cell, and therefore realize low-power operation. Here, we demonstrate that a write energy can be reduced to about ~53.7 fJ in a cell with ~3 nm-wide graphene nanoribbon (GNR) as edge-contact, whose cross-sectional area is only ~1 nm2. It is found that the cycle endurance exhibits an obvious dependence on the bias polarity in the cell with structure asymmetry. If a positive bias was applied to graphene electrode, the endurance can be extended at least one order longer than the case with reversal of polarity. The work represents a great technological advance for the low power PCRAM and could benefit for in-memory computing in future.Comment: 14 pages, 4 figure

Fast and reliable storage using a 5 bit, nonvolatile photonic memory cell

This is the final version. Available from Optical Society of America via the DOI in this record.Optically storing and addressing data on photonic chips is of particular interest as such capability would eliminate optoelectronic conversion losses in data centers. It would also enable on-chip non-von Neumann photonic computing by allowing multinary data storage with high fidelity. Here, we demonstrate such an optically addressed, multilevel memory capable of storing up to 34 nonvolatile reliable and repeatable levels (over 5 bits) using the phase change material Ge2Sb2Te5 integrated on a photonic waveguide. Crucially, we demonstrate for the first time, to the best of our knowledge, a technique that allows us to program the device with a single pulse regardless of the previous state of the material, providing an order of magnitude improvement over previous demonstrations in terms of both time and energy consumption. We also investigate the influence of write-and-erase pulse parameters on the single-pulse recrystallization, amorphization, and readout error in our multilevel memory, thus tailoring pulse properties for optimum performance. Our work represents a significant step in the development of photonic memories and their potential for novel integrated photonic applications.Engineering and Physical Sciences Research Council (EPSRC)European CommissionDeutsche Forschungsgemeinschaft (DFG)Horizon 2020 Framework Programme (H2020