Materials and processes issues in fine pitch eutectic solder flip chip interconnection

New product designs within the electronics packaging industry continue to demand interconnects at microscopic geometry, both at the Integrated Circuit (IC) and supporting board level, thereby creating numerous manufacturing challenges. Flip Chip On Board (FCOB) applications are currently being driven by competitive manufacturing costs and the need for higher volume and robust production capabilities. One of today’s low cost FCOB solutions has emerged as an extension of the existing infrastructure for Surface Mount Technology (SMT) and combines an Under Bump Metallisation (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition, have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of such bumps at different geometries. The effect of precise control of the tolerances of squeegees, stencils and wafer fixtures was examined to enable the optimisation of the materials, processes and tooling for reduction of bumping defects

Materials and processes issues in fine pitch eutectic solder flip chip interconnection

New product designs within the electronics packaging industry continue to demand interconnects at shrinking geometry, both at the integrated circuit and supporting circuit board substrate level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by the need for reduced manufacturing costs and higher volume robust production capability. One of today’s low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology and combines an under bump metallization (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of said bumps at different geometries. The effect of precise control of tolerances in squeegees, stencils and wafer fixtures was examined to enable the optimization of the materials, processes, and tooling for reduction of bumping defects

Microstructural and mechanical characteristics of micro-scale intermetallic compounds interconnections

Following the continually increasing demand for high-density interconnection and multilayer packaging for chips, solder bump size has decreased significantly over the years, this has led to some challenges in the reliability of interconnects. This thesis presents research into the resulting effects of miniaturization on the interconnection with Sn-solder, especially focusing on the full intermetallics (IMCs) micro-joints which appear in the 3D IC stacking packaging. Thereby, systematic studies have been conducted to study the microstructural evolution and reliability issues of Cu-Sn and Cu-Sn-Ni IMCs micro-joints. (1) Phenomenon of IMCs planar growth: The planar IMCs interlayer was asymmetric and composed of (Cu,Ni)6Sn5 mainly in Ni/Sn (2.5~5 µm)/Cu interconnect. Meanwhile, it was symmetric two-layer structure in Cu/Sn (2.5~5 µm)/Cu interconnect with the Cu3Sn fine grains underneath Cu6Sn5 cobblestone-shape-like grains for each IMCs layer. Besides, it is worth noticing that the appearance of Cu-rich whiskers (the mixture of Cu/Cu2O/SnOx/Cu6Sn5) could potentially lead to short-circuit in the cases of ultra-fine (<10 µm pitch) interconnects for the miniaturization of electronics devices. (2) Microstructural evolution process of Cu-Sn IMCs micro-joint: The simultaneous solidification of IMCs interlayer supressed the scalloped growth of Cu6Sn5 grains in Cu/Sn (2.5 µm)/Cu interconnect during the transient liquid phase (TLP) soldering process. The growth factor of Cu3Sn was in the range of 0.29~0.48 in Cu-Cu6Sn5 diffusion couple at 240~290 °C, which was impacted significantly by the type of substrates. And the subsequent homogenization process of Cu3Sn grains was found to be consistent with the description of flux-driven ripening (FDR) theory. Moreover, Kirkendall voids appeared only in the Cu3Sn layer adjacent to Cu-plated substrate, and this porous Cu3Sn micro-joint was mechanically robust during the shear test. (3) Microstructural evolution of Cu-Sn-Ni IMCs micro-joint: There was obvious inter-reaction between the interfacial reactions in Ni/Sn (1.5 µm)/Cu interconnect. The growth factor of (Cu,Ni)3Sn on Cu side was about 0.36 at 240 °C, and the reaction product on Ni side was changed from Ni3Sn4 into (Cu,Ni)6Sn5 with the increase of soldering temperature. In particular, the segregation of Ni atoms occurred along with phase transformation at 290 °C and thereby stabilized the (Cu,Ni)6Sn5 phase for the high Ni content of 20 at.%. (4) Micro-mechanical characteristics of Cu-Sn-Ni IMCs micro-joint: The Young s modulus and hardness of Cu-Sn-Ni IMCs were measured by nanoindentation test, such as 160.6±3.1 GPa/ 7.34±0.14 GPa for (Cu,Ni)6Sn5 and 183.7±4.0 GPa/ 7.38±0.46 GPa for (Cu,Ni)3Sn, respectively. Besides, in-situ nano-compression tests have been conducted on IMCs micro-cantilevers, the fracture strength turns out to be 2.46 GPa. And also, the ultimate tensile stress was calculated to be 2.3±0.7 GPa from in-situ micro-bending tests, which is not sensitive with the microstructural change of IMCs after dwelling at 290 °C

Properties and behaviour of Pb-free solders in flip-chip scale solder interconnections

Due to pending legislations and market pressure, lead-free solders will replace Sn–Pb solders in 2006. Among the lead-free solders being studied, eutectic Sn–Ag, Sn–Cu and Sn–Ag–Cu are promising candidates and Sn–3.8Ag–0.7Cu could be the most appropriate replacement due to its overall balance of properties. In order to garner more understanding of lead-free solders and their application in flip-chip scale packages, the properties of lead free solders, including the wettability, intermetallic compound (IMC) growth and distribution, mechanical properties, reliability and corrosion resistance, were studied and are presented in this thesis. [Continues.

Electrodeposition of indium bumps for ultrafine pitch interconnections

Microelectronics integration continuously follows the trend of miniaturisation for which the technologies enabling fine pitch interconnection are in high demand. The recent advancement in the assembly of Hybrid Pixel Detectors, a high resolution detecting and imaging device, is an example of where novel materials and processes can be applied for ultra-fine pitch interconnections. For this application, indium is often used for the fine pitch bump bonding process due to its unique properties that make it especially suitable, in particular in a cryogenic environment where some types of detector have to serve. Indium bumps are typically fabricated through vacuum evaporation at the wafer level; however, this thesis investigates an alternative low cost manufacturing process at the wafer scale for the deposition of indium micro-bumps through electroplating. The work has placed its emphasis on the requirements of future technologies which will enable a low temperature ( 40,000 IOs/cm2) with a high throughput and high production yield. This research is a systematic investigation of the wafer-scale indium bumping process through electrodeposition using indium sulphamate solution. An intensive experimental study of micro-bump formation has been carried out to elaborate the effects of two of the main electroplating factors that can significantly influence the quality of bumps in the course of electrodeposition, namely the current distribution and mass transport. To adjust the current density distribution, various waveforms of current input, including direct current (DC), unipolar pulse current and bipolar pulse reverse current, were employed in the experiments. To assist mass transportation prior to or during electroplating, acoustic agitation including ultrasonic agitation at 30 kHz frequency as well as megasonic agitation at 1 MHz, were utilised. The electrochemical properties of the indium sulphamate solution were first investigated using non-patterned plain substrates prior to indium bumping trials. This provided understanding of the microstructural characteristics of indium deposits produced by electroplating and, through cathodic polarisation measurements, the highest current density suitable for electrodeposition was achieved as approximately 30 mA/cm2 when electroplating was carried out at room temperature and with no agitation applied. The typical surface morphology of DC electroplated indium contained a granular structure with a surface feature size as large as 10 µm. Pulse and pulse reverse electroplating significantly altered the surface morphology of the deposits and the surface became much smoother. By introducing acoustic agitation, the current density range suitable for electrodeposition could be significantly expanded due to the greater mass transfer, which led to a higher speed of deposition with high current efficiency. Wafer-scale indium bumping (15 µm to 25 µm diameter) at a minimum pitch size of 25 µm was successfully developed through electroplating trials with 3 inch test wafers and subsequently applied onto the standard 4 inch wafers. The results demonstrate the capability of electroplating to generate high quality indium bumps with ultrafine pitch at a high consistency and yield. To maximise the yield, pre-wetting of the ultrafine pitch photoresist patterns by both ultrasonic or megasonic agitation is essential leading to a bumping yield up to 99.9% on the wafer scale. The bump profiles and their uniformity at both the wafer and pattern scale were measured and the effects of electrodeposition regimes on the bump formation evaluated. The bump uniformity and microstructure at the feature scale were also investigated by cross-sectioning the electroplated bumps from different locations on the wafers. The growth mechanism of indium bumps were proposed on the basis of experimental observation. It was found that the use of a conductive current thief ring can homogenise the directional bump uniformity when the electrical contact is made asymmetrically, and improve the overall uniformity when the electrical contact is made symmetrically around the periphery of the wafer. Both unipolar pulse electroplating and bipolar pulse reverse electroplating improved the uniformity of the bump height at the wafer scale and pattern scale, and the feature scale uniformity could be significantly improved by pulse reverse electroplating. The best uniformity of 13.6% for a 4 inch wafer was achieved by using pulse reverse electroplating. The effect of ultrasonic agitation on the process was examined, but found to cause damage to the photoresist patterns if used for extended periods and therefore not suitable for use throughout indium bumping. Megasonic agitation enabled high speed bumping without sacrifice of current efficiency and with little damage to the photoresist patterns. However, megasonic agitation tended to degrade some aspects of wafer scale uniformity and should therefore be properly coupled with other electroplating parameters to assist the electroplating process.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Peripheral soldering of flip chip joints on passive RFID tags

Flip chip is the main component of a RFID tag. It is used in billions each year in electronic packaging industries because of its small size, high performance and reliability as well as low cost. They are used in microprocessors, cell phones, watches and automobiles. RFID tags are applied to or incorporated into a product, animal, or person for identification and tracking using radio waves. Some tags can be read from several meters away or even beyond the line of sight of the reader. Passive RFID tags are the most common type in use that employ external power source to transmit signals. Joining chips by laser beam welding have wide advantages over other methods of joining, but they are seen limited to transparent substrates. However, connecting solder bumps with anisotropic conductive adhesives (ACA) produces majority of the joints. A high percentage of them fail in couple of months, particularly when exposed to vibration. In the present work, failure of RFID tags under dynamic loading or vibration was studied; as it was identified as one of the key issue to explore. Earlier investigators focused more on joining chip to the bump, but less on its assembly, i.e., attaching to the substrate. Either of the joints, between chip and bump or between antenna and bump can fail. However, the latter is more vulnerable to failure. Antenna is attached to substrate, relatively fixed when subjected to oscillation. It is the flip chip not the antenna moves during vibration. So, the joint with antenna suffers higher stresses. In addition to this, the strength of the bonding agent i.e., ACA also much smaller compared to the metallic bond at the other end of the bump. Natural frequency of RFID tags was calculated both analytically and numerically, found to be in kilohertz range, high enough to cause resonance. Experimental investigations were also carried out to determine the same. However, the test results for frequency were seen to be in hundred hertz range, common to some applications. It was recognized that the adhesive material, commonly used for joining chips, was primarily accountable for their failures. Since components to which the RFID tags are attached to experience low frequency vibration, chip joints fail as they face resonance during oscillation. Adhesives having much lower modulus than metals are used for attaching bumps to the substrate antennas, and thus mostly responsible for this reduction in natural frequency. Poor adhesive bonding strength at the interface and possible rise in temperature were attributed to failures under vibration. In order to overcome the early failure of RFID tag joints, Peripheral Soldering, an alternative chip joining method was devised. Peripheral Soldering would replace the traditional adhesive joining by bonding the peripheral surface of the bump to the substrate antenna. Instead of joining solder bump directly to the antenna, holes are to be drilled through antenna and substrate. S-bond material, a less familiar but more compatible with aluminum and copper, would be poured in liquid form through the holes on the chip pad. However, substrates compatible to high temperature are to be used; otherwise temperature control would be necessary to avoid damage to substrate. This S-bond would form metallic joints between chip and antenna. Having higher strength and better adhesion property, S-bond material provides better bonding capability. The strength of a chip joined by Peripheral Soldering was determined by analytical, numerical and experimental studies. Strength results were then compared to those of ACA. For a pad size of 60 micron on a 0.5 mm square chip, the new chip joints with Sbond provide an average strength of 0.233N analytically. Numerical results using finite element analysis in ANSYS 11.0 were about 1% less than the closed form solutions. Whereas, ACA connected joints show the maximum strength of 0.113N analytically and 0.1N numerically. Both the estimates indicate Peripheral Soldering is more than twice stronger than adhesive joints. Experimental investigation was carried out to find the strength attained with S-bond by joining similar surfaces as those of chip pad and antenna, but in larger scale due to limitation in facilities. Results obtained were moderated to incorporate the effect of size. Findings authenticate earlier predictions of superior strengths with S-bond. A comparison with ACA strength, extracted from previous investigations, further indicates that S-bond joints are more than 10 times stronger. Having higher bonding strength than in ACA joints, Peripheral Soldering would provide better reliability of the chip connections, i.e., RFID tags. The benefits attained would pay off complexities involved in tweaking

Développement d’un procédé d’électrodéposition séquentielle pour fabrication des microbilles à haute densité

Aujourd’hui l’industrie des semiconducteurs aborde une époque requérant le couplage de l’innovation au niveau de l'assemblage avec la mise à l’échelle des dispositifs. Cette dernière n’est plus l’élément clé qui propulse l’évolution technologique à cause de l’énorme investissement requis vis-à-vis sa rentabilité qui devient de plus en plus limitée. Avec la réorientation de l’intérêt de la majorité des acteurs vers l’innovation au niveau des assemblages, cette thèse s’inscrit dans un contexte d’amélioration de la fiabilité des assemblages de larges puces renversées pour le calul haute performance à travers le développement des microbilles de brasures à faible coût et de métallurgie optimisée. Des microbilles de brasure à faible coût et hétérogènes sont proposées comme une approche simple qui présente des bénéfices métallurgiques et économiques. D’une part, l’électrodéposition séquentielle des couches de Sn et Ag pures au lieu d’alliage est réalisée à un faible coût d’acquisition et avec une simplicité de maintenance. D’une autre part, la même installation d’électrodéposition de Sn et Ag purs peut servir à la fabrication d’une multitude de brasures avec différentes teneurs en Ag. Malgré le besoin d’une standardisation des procédés de fabrication des microbilles, les motivations citées précédemment peuvent constituer un facteur d’attraction pour l’industrie afin de l’adopter comme alternative à l’électrodéposition conventionnelle des alliages. En plus de son faible coût, l’approche de fabrication des microbilles par électrodéposition séquentielle amène une flexibilité métallurgique avec l’utilisation d’une barrière qui limite la diffusion d’Ag. Cette dernière résulte en une microbille de brasure unique, qui peut à la fois i) avoir une structure hétérogène avec une faible teneur en Ag dont la ductilité élevée est maintenue à proximité des couches fragiles de la métallisation de la puce lors des étapes de l’assemblage; ii) avoir une forme en pilier dont des bénéfices sont similaires à ceux du pilier en Cu en évitant les effets néfastes de sa rigidité sur les couches du BEOL. Les différentes étapes de fabrication des microbilles de brasure ont été développées en se limitant à des procédés qui peuvent être intégrés facilement dans un environnement de production industrielle. La manipulation de la métallurgie des joints de brasure a été réalisée avec succès en démontrant une structure hétérogène unique de brasure dans un assemblage de puces renversées

Novel Photostructurable Polymer for On-Board Optical Interconnects Enabled by Femtosecond Direct Laser Writing

Die integrierte Optik hat sich als vielversprechende Lösung für elektronische Verbindungen erwiesen, die eine hohe Bandbreitendichte und einen geringen Stromverbrauch ermöglicht. Seit kurzem ist es möglich photochemische und physikalische Reaktionen auf ein Mikrovolumen zu begrenzen. Dies hat der optischen Verbindungstechnik unter Verwendung von Glas oder Polymer eine zusätzliche Dimension verliehen. Dreidimensionale Wellenleiter können das optische Signal zwischen Blöcken aller Dimensionen verbinden, kombinieren oder aufteilen. Die Erhöhung des Brechungsindex ist jedoch immer noch eine Herausforderung für die Herstellung stabiler Freiform- und monomodaler Wellenleiter mit dreidimensionaler Ausdehnung, welche sich innerhalb der Platine befinden. Diese Dissertation stellt ein neues Konzept vor, um dieser Herausforderung zu begegnen, indem direktes Femtosekunden-Laserschreiben in Polymer und externe Diffusion eines gasförmigen Monomers verwendet wird. Direktes Laserschreiben mit Zwei-Photonen-Absorption wurde verwendet, um die Vernetzung entlang eines vorher definierten Pfades zur Bildung des Wellenleiterkerns zu initiieren. Es wurde ein ausreichender Brechungsindexkontrast erzeugt, um gaußförmige Strahlen mit einem Modus zu führen. Feature-Größen konnten durch Variieren der Scangeschwindigkeit und der Laserintensität linear angepasst werden. Dieses Herstellungsverfahren erfordert nur eine Schicht eines einzelnen Materials ohne Masken-, Kontakt- oder Nassbearbeitung. Durch Verwendung dieser neuartigen Methode wurden dreidimensionale optische Wellenleiter-Arrays, Fan-in/Fan-out- und Splitter-Strukturen hergestellt. Dreidimensionale freiforme Wellenleiter haben ein hohes Potential zur Verbesserung der Packungsdichte und Flexibilität optischer Verbindungen auf Platinenebene