Multiple objective optimisation of data and control paths in a behavioural silicon compiler

The objective of this research was to implement an 'intelligent' silicon compiler that provides the ability to automatically explore the design space and optimise a design, given as a behavioural description, with respect to multiple objectives. The objective has been met by the implementation of the MOODS Silicon Compiler. The user submits goals or objectives to the system which automatically finds near optimal solutions. As objectives may be conflicting, trade-offs between synthesis tasks are essential and consequently their simultaneous execution must occur. Tasks are decomposed into behaviour preserving transformations which, due to their completeness, can be applied in any sequence to a multi-level representation of the design. An accurate evaluation of the design is ensured by feeding up technology dependent information to a cost function. The cost function guides the simulated annealing algorithm in applying transformations to iteratively optimise the design. The simulated annealing algorithm provides an abstractness from the transformations and designer's objectives. This abstractness avoids the construction of tailored heuristics which pre-program trade-offs into a system. Pre-programmed trade-offs are used in most systems by assuming a particular shape to the trade-off curve and are inappropriate as trade-offs are technology dependent. The lack of pre-programmed trade-offs in the MOODS system allows it to adapt to changes in technology or library cells. The choice of cells and their subsequent sharing are based on the user's criteria expressed in the cost function, rather than being pre-programmed into the system. The results show that implementations created by MOODS are better than or equal to those achieved by other systems. Comparisons with other systems highlighted the importance of specifying all of a design's data as the lack of data misrepresents the design leading to misleading comparisons. The MOODS synthesis system includes an efficient method for automated design space exploration where a varied set of near optimal implementations can be produced from a single behavioural specification. Design space exploration is an important aspect of designing by high-level synthesis and in the development of synthesis systems. It allows the designer to obtain a perspicuous characterization of a design's design space allowing him to investigate alternative designs

A Graph Rewriting Approach for Transformational Design of Digital Systems

Transformational design integrates design and verification. It combines “correctness by construction” and design creativity by the use of pre-proven behaviour preserving transformations as design steps. The formal aspects of this methodology are hidden in the transformations. A constraint is the availability of a design representation with a compositional formal semantics. Graph representations are useful design representations because of their visualisation of design information. In this paper graph rewriting theory, as developed in the last twenty years in mathematics, is shown to be a useful basis for a formal framework for transformational design. The semantic aspects of graphs which are no part of graph rewriting theory are included by the use of attributed graphs. The used attribute algebra, table algebra, is a relation algebra derived from database theory. The combination of graph rewriting, table algebra and transformational design is new

Translation of VHDL Sequential Statements

VHDL is one of the most popular languages used in logic synthesis tools. It has variety of statements which make it powerful and flexible tool. But, as the result, it is rather difficult to create a compiler of VHDL language, especially the one which will be used in a logic synthesis. There is little information about translation algorithms used to generate hardware representation from VHDL sources. The algorithms for few sequential statements of VHDL language are developed. Apart from the algorithms themselves the paper presents a lot of information about translation process itself and all possible problems which may occur during it. Proposed solution was implemented in a compilerwhich uses Boolean equations as an output format. The paper includes results of tests which were performed to check practical usability boundaries of proposed algorithms.VHDL – один из наиболее популярных языков, используемых в средствах логического синтеза. Он содержит множество операторов, которые обеспечивают его мощность и гибкость, поэтому создание компилятора языка VHDL, ориентированного на использование в логическом синтезе, – сложная задача. Информации об алгоритмах трансляции, поступающей от разработчиков VHDL, недостаточно для создания технических средств. Разработаны такие алгоритмы для некоторых последовательностных операторов языка VHDL. Предложенное решение реализовано в компиляторе, использующем логические уравнения как выходной формат. Приведены результаты тестов, выполненных для проверки границ практической применимости предложенных алгоритмов.VHDL – одна з найпопулярніших мов, які використовують у засобах логічного синтезу. Вона вміщує безліч операторів, що забезпечують ії потужність та гнучкість, тому створення компілятора мови VHDL, орієнтованого на використання у логічному синтезі є складною задачею. Інформація про алгоритми трансляції, що надходить від розробників VHDL, є недостатньою для створення технічних засобів. Розроблено алгоритми для деяких послідовнісних операторів мови VHDL. Запропоноване рішення реалізовано у компіляторі, який використовує логічні рівняння як вихідний формат. Наведено результати тестів, виконаних для перевірки меж можливості практичного використання запропонованих алгоритмів

STRICT: a language and tool set for the design of very large scale integrated circuits

PhD ThesisAn essential requirement for the design of large VLSI circuits is a design methodology which would allow the designer to overcome the complexity and correctness issues associated with the building of such circuits. We propose that many of the problems of the design of large circuits can be solved by using a formal design notation based upon the functional programming paradigm, that embodies design concepts that have been used extensively as the framework for software construction. The design notation should permit parallel, sequential, and recursive decompositions of a design into smaller components, and it should allow large circuits to be constructed from simpler circuits that can be embedded in a design in a modular fashion. Consistency checking should be provided as early as possible in a design. Such a methodology would structure the design of a circuit in much the same way that procedures, classes, and control structures may be used to structure large software systems. However, such a design notation must be supported by tools which automatically check the consistency of the design, if the methodology is to be practical. In principle, the methodology should impose constraints upon circuit design to reduce errors and provide' correctness by construction' . It should be possible to generate efficient and correct circuits, by providing a route to a large variety of design tools commonly found in design systems: simulators, automatic placement and routing tools, module generators, schematic capture tools, and formal verification and synthesis tools