150 research outputs found
ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ ๊ธฐ๋ฐ ๊ธฐ์ค ์ฃผํ์๋ฅผ ์ฌ์ฉํ์ง ์๋ ํด๋ก ๋ฐ ๋ฐ์ดํฐ ๋ณต์ ํ๋ก์ ์ค๊ณ ๋ฐฉ๋ฒ๋ก
ํ์๋
ผ๋ฌธ(๋ฐ์ฌ) -- ์์ธ๋ํ๊ต๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2022. 8. ์ ๋๊ท .In this thesis, a design of a high-speed, power-efficient, wide-range clock and data recovery (CDR) without a reference clock is proposed. A frequency acquisition scheme using a stochastic frequency detector (SFD) based on the Alexander phase detector (PD) is utilized for the referenceless operation. Pat-tern histogram analysis is presented to analyze the frequency acquisition behavior of the SFD and verified by simulation. Based on the information obtained by pattern histogram analysis, SFD using autocovariance is proposed. With a direct-proportional path and a digital integral path, the proposed referenceless CDR achieves frequency lock at all measurable conditions, and the measured frequency acquisition time is within 7ฮผs. The prototype chip has been fabricated in a 40-nm CMOS process and occupies an active area of 0.032 mm2. The proposed referenceless CDR achieves the BER of less than 10-12 at 32 Gb/s and exhibits an energy efficiency of 1.15 pJ/b at 32 Gb/s with a 1.0 V supply.๋ณธ ๋
ผ๋ฌธ์ ๊ธฐ์ค ํด๋ญ์ด ์๋ ๊ณ ์, ์ ์ ๋ ฅ, ๊ด๋์ญ์ผ๋ก ๋์ํ๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก์ ์ค๊ณ๋ฅผ ์ ์ํ๋ค. ๊ธฐ์ค ํด๋ญ์ด ์๋ ๋์์ ์ํด์ ์๋ ์ฐ๋ ์์ ๊ฒ์ถ๊ธฐ์ ๊ธฐ๋ฐํ ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ๋ฅผ ์ฌ์ฉํ๋ ์ฃผํ์ ํ๋ ๋ฐฉ์์ด ์ฌ์ฉ๋๋ค. ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ์ ์ฃผํ์ ์ถ์ ์์์ ๋ถ์ํ๊ธฐ ์ํด ํจํด ํ์คํ ๊ทธ๋จ ๋ถ์ ๋ฐฉ๋ฒ๋ก ์ ์ ์ํ์๊ณ ์๋ฎฌ๋ ์ด์
์ ํตํด ๊ฒ์ฆํ์๋ค. ํจํด ํ์คํ ๊ทธ๋จ ๋ถ์์ ํตํด ์ป์ ์ ๋ณด๋ฅผ ๋ฐํ์ผ๋ก ์๊ธฐ๊ณต๋ถ์ฐ์ ์ด์ฉํ ํต๊ณ์ ์ฃผํ์ ๊ฒ์ถ๊ธฐ๋ฅผ ์ ์ํ๋ค. ์ง์ ๋น๋ก ๊ฒฝ๋ก์ ๋์งํธ ์ ๋ถ ๊ฒฝ๋ก๋ฅผ ํตํด ์ ์๋ ๊ธฐ์ค ํด๋ญ์ด ์๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก๋ ๋ชจ๋ ์ธก์ ๊ฐ๋ฅํ ์กฐ๊ฑด์์ ์ฃผํ์ ์ ๊ธ์ ๋ฌ์ฑํ๋ ๋ฐ ์ฑ๊ณตํ์๊ณ , ๋ชจ๋ ๊ฒฝ์ฐ์์ ์ธก์ ๋ ์ฃผํ์ ์ถ์ ์๊ฐ์ 7ฮผs ์ด๋ด์ด๋ค. 40-nm CMOS ๊ณต์ ์ ์ด์ฉํ์ฌ ๋ง๋ค์ด์ง ์นฉ์ 0.032 mm2์ ๋ฉด์ ์ ์ฐจ์งํ๋ค. ์ ์ํ๋ ํด๋ญ ๋ฐ ๋ฐ์ดํฐ ๋ณต์ํ๋ก๋ 32 Gb/s์ ์๋์์ ๋นํธ์๋ฌ์จ 10-12 ์ดํ๋ก ๋์ํ์๊ณ , ์๋์ง ํจ์จ์ 32Gb/s์ ์๋์์ 1.0V ๊ณต๊ธ์ ์์ ์ฌ์ฉํ์ฌ 1.15 pJ/b์ ๋ฌ์ฑํ์๋ค.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 THESIS ORGANIZATION 13
CHAPTER 2 BACKGROUNDS 14
2.1 CLOCKING ARCHITECTURES IN SERIAL LINK INTERFACE 14
2.2 GENERAL CONSIDERATIONS FOR CLOCK AND DATA RECOVERY 24
2.2.1 OVERVIEW 24
2.2.2 JITTER 26
2.2.3 CDR JITTER CHARACTERISTICS 33
2.3 CDR ARCHITECTURES 39
2.3.1 PLL-BASED CDR โ WITH EXTERNAL REFERENCE CLOCK 39
2.3.2 DLL/PI-BASED CDR 44
2.3.3 PLL-BASED CDR โ WITHOUT EXTERNAL REFERENCE CLOCK 47
2.4 FREQUENCY ACQUISITION SCHEME 50
2.4.1 TYPICAL FREQUENCY DETECTORS 50
2.4.1.1 DIGITAL QUADRICORRELATOR FREQUENCY DETECTOR 50
2.4.1.2 ROTATIONAL FREQUENCY DETECTOR 54
2.4.2 PRIOR WORKS 56
CHAPTER 3 DESIGN OF THE REFERENCELESS CDR USING SFD 58
3.1 OVERVIEW 58
3.2 PROPOSED FREQUENCY DETECTOR 62
3.2.1 MOTIVATION 62
3.2.2 PATTERN HISTOGRAM ANALYSIS 68
3.2.3 INTRODUCTION OF AUTOCOVARIANCE TO STOCHASTIC FREQUENCY DETECTOR 75
3.3 CIRCUIT IMPLEMENTATION 83
3.3.1 IMPLEMENTATION OF THE PROPOSED REFERENCELESS CDR 83
3.3.2 CONTINUOUS-TIME LINEAR EQUALIZER (CTLE) 85
3.3.3 DIGITALLY-CONTROLLED OSCILLATOR (DCO) 87
3.4 MEASUREMENT RESULTS 89
CHAPTER 4 CONCLUSION 99
APPENDIX A DETAILED FREQUENCY ACQUISITION WAVEFORMS OF THE PROPOSED SFD 100
BIBLIOGRAPHY 108
์ด ๋ก 122๋ฐ
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Digital PLL for ISM applications
In modern transceivers, a low power PLL is a key block. It is known that with the
evolution of technology, lower power and high performance circuitry is a challenging
demand.
In this thesis, a low power PLL is developed in order not to exceed 2mW of total power
consumption. It is composed by small area blocks which is one of the main demands.
The blocks that compose the PLL are widely abridged and the final solution is shown,
showing why it is employed. The VCO block is a Current-Starved Ring Oscillator with
a frequency range from 400MHz to 1.5GHz, with a 300ฮผW to approximately 660ฮผW
power consumption. The divider is composed by six TSPC D Flip-Flop in series, forming
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as expected. It also has a total power consumption of 1.3mW, therefore fulfilling all the
specifications.
The main contributions of this thesis are that this PLL can be applied in ISM applications
due to its covering frequency range and low cost 130nm CMOS technology
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