Quasi Switched Capacitor based integrated Boost Series Parallel Fly-back Converter for energy Storage Applications

711-715A quasi-Switched Capacitor technique (QSC) is used to control the switch in Interconnected Boost Series Parallel Fly-Back Converter (IBSPFC). The QSC based IBSPFC does not require any snubber circuits for all the MOSFET switches presented at primary and secondary side and power can also be transferred even if one the winding gets damage. The primary side winding of the fly-back transformer is coupled in series across with bulk capacitor to minimize switch voltage stress and the secondary winding of the 1:1 fly-back transformer is coupled with dc voltage source, three switches and capacitor which forms a Quasi switched capacitor technique. Working techniques of quasi-switched capacitor with IBSPFC have been introduced. A 75v input, 100v output and DC-DC isolated Converter switching at frequency of 100 kHz is modeled using FPGA SPARTAN6LX9 and experimental results have been presented

A novel method for fatigue testing of MEMS devices containing movable elements

In this paper we present an electronic circuit for position or capacitance estimation of MEMS electrostatic actuators based on a switched capacitor technique. The circuit uses a capacitive divider configuration composed by a fixed capacitor and the variable capacitance of the electrostatic actuator for generating a signal that is a function of the input voltage and capacitive ratio. The proposed circuit can be used to actuate and to sense position of an electrostatic MEMS actuator without extra sensing elements. This approach is compatible with the requirements of most analog feedback systems and the circuit topology of pulsed digital oscillators (PDO).Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/EDA-Publishing

Design of the 12-bit Delta-Sigma Modulator using SC Technique for Vibration Sensor Output Processing

The work deals with the design of the 12-bit Delta-Sigma modulator using switched capacitors (SC) technique. The modulator serves to vibration sensor output processing. The first part describes the Delta-Sigma modulator parameters definition. Results of the proposed topology ideal model were presented as well. Next, the Delta-Sigma modulator circuitry on the transistor level was done. The ONSemiconductor I2T100 0.7 um CMOS technology was used for design. Then, the Delta-Sigma modulator nonidealities were simulated and implemented into the MATLAB ideal model of the modulator. The model of real Delta-Sigma modulator was derived. Consequently, modulator coefficients were optimized. Finally, the corner analysis of the Delta-Sigma modulator with the optimized coefficients was simulated. The value of SNDR = 82.2 dB (ENOB = 13.4 bits) was achieved

A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator

In low-power VLSI design applications non-linearity and harmonics are a major dominant factor which affects the performance of the ADC. To avoid this, the new architecture of voltage-controlled oscillator (VCO) was required to solve the non-linearity issues and harmonic distortion. In this work, a 12-bit, 200MS/s low power delta-sigma analog to digital converter (ADC) VCO based quantizer was designed using switched capacitor technique. The proposed technique uses frequency to current conversion technique as a linearization method to reduce the non-linearity issue. Simulation result show that the proposed 12-bit delta-sigma ADC consumes the power of 2.68 mW and a total area of 0.09 mm² in 90 nm CMOS process

Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator

Chaos in a Switched-Capacitor Circuit

We report chaotic phenomena observed from a simple nonlinear switched-capacitor circuit. The experimentally measured bifurcation tree diagram reveals a period-doubling route to chaos. This circuit is described by a first-order discrete equation which can be transformed into the logistic map whose chaotic dynamics is well known.National Science Foundation ECS-8542885Comisión Interministerial de Ciencia y Tecnología 0245/81Office of Naval Research under Contract NOOO14-76-C-057

Design and development of sigma-delta AD converter in switched capacitor technique

Práce se zabývá návrhem nového sigma-delta převodníku vyššího řádu využívajícího techniku spínaných kapacitorů. V programu MATLAB SIMULINK byl navržen a simulován ideální a reálný model architektury modulátoru sigma-delta 3. řádu. Jednotlivé bloky modulátoru sigma-delta 3. řádu byly navrženy na tranzistorové úrovni v technologii CMOS na základě výsledků simulací reálného modelu architektury v programu MATLAB SIMULINK. Byl navržen plně diferenční operační zesilovač, integrátor využívající techniku spínaných kapacitorů, sumační zesilovač, komparátor, jednobitový převodník DA a generátor řidicích hodinových signálů. Obvodové řešení modulátoru sigma-delta 3. řádu bylo simulováno v prostředí CADENCE. U obvodu operačního zesilovač a integrátoru byl vytvořen layout. Pomocí programu MATLAB byl navržen také decimační filtr.The work deals with the design of novel high order sigma-delta AD converter using switched-capacitors approach. Model of the ideal and real architecture of the third order sigma-delta modulator was designed in MATLAB SIMULINK. The comparison of the ideal and real model of sigma delta architecture is described in this thesis. On the basis of simulation results in MATLAB SIMULINK the stages of modulator on transistors level in CMOS technology were designed. Fully differential operational amplifier, switched capacitor integrator, summing amplifier, comparator, one bit digital to analog converter and nonoverlapping clock generator were designed. The circuit of third order sigma-delta modulator was simulated in CADENCE. Layout of operational amplifier and switched capacitor integrator was made. Through the use of MATLAB was designed decimation filter as well.

High-Performance Bioinstrumentation for Real-Time Neuroelectrochemical Traumatic Brain Injury Monitoring

Traumatic brain injury (TBI) has been identified as an important cause of death and severe disability in all age groups and particularly in children and young adults. Central to TBIs devastation is a delayed secondary injury that occurs in 30–40% of TBI patients each year, while they are in the hospital Intensive Care Unit (ICU). Secondary injuries reduce survival rate after TBI and usually occur within 7 days post-injury. State-of-art monitoring of secondary brain injuries benefits from the acquisition of high-quality and time-aligned electrical data i.e., ElectroCorticoGraphy (ECoG) recorded by means of strip electrodes placed on the brains surface, and neurochemical data obtained via rapid sampling microdialysis and microfluidics-based biosensors measuring brain tissue levels of glucose, lactate and potassium. This article progresses the field of multi-modal monitoring of the injured human brain by presenting the design and realization of a new, compact, medical-grade amperometry, potentiometry and ECoG recording bioinstrumentation. Our combined TBI instrument enables the high-precision, real-time neuroelectrochemical monitoring of TBI patients, who have undergone craniotomy neurosurgery and are treated sedated in the ICU. Electrical and neurochemical test measurements are presented, confirming the high-performance of the reported TBI bioinstrumentation

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for monolithie active pixel sensors

A 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors

International audienceA 4 bit very low power and low incoming signal analog to digital converter (ADC) using a double sampling switched capacitor technique, designed for use in CMOS monolithic active pixels sensor readout, has been implemented in 0.35μm CMOS technology. A non-resetting sample and hold stage is integrated to amplify the incoming signal by 4. This first stage compensates both the amplifier offset effect and the input common mode voltage fluctuations. The converter is composed of a 2.5 bit pipeline stage followed by a 2 bit flash stage. This prototype consists of 4 ADC double-channels; each one is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supply voltage. A bias pulsing stage is integrated in the circuit. Therefore, the analog part is switched OFF or ON in less than 1μs. The size for the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixel columns, each one is 20μm wide