Biquadratic Filter Applications Using a Fully-Differential Active-Only Integrator

A new class of active filters, real active-only filters is described and possible implementation issues of these filters are discussed. To remedy these issues, a fully-differential active-only integrator block built around current controlled current conveyors is presented. The integration frequency of the proposed circuit is adjustable over a wide frequency range. As an application, a real active-only filter based on the classical two-integrator loop topology is presented and designed. The feasibility of this filter in a 0.35µm CMOS process is verified through SPECTRE simulation program in the CADENCE design tool

Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications

Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from benefits of rapid prototyping. This forces them to expensive and lengthy custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitations come from two directions: commercial Field Programmable Analog Arrays (FPAA) have limited variability in the components offered on-chip; and they are only qualified for best case scenarios for military grade (-55C to +125C). In order to avoid huge overheads, there is a growing trend towards avoiding thermal and radiation protection by developing extreme environment electronics, which maintain correct operation while exposed to temperature extremes (-180degC to +125degC). This paper describes a recent FPAA design, the Self-Reconfigurable Analog Array (SRAA) developed at JPL. It overcomes both limitations, offering a variety of analog cells inside the array together with the possibility of self-correction at extreme temperatures

Bioimpedance Sensor

A bioimpdance senor to measure the impedance of a human body. Completed as part of the engineering Senior Design Projec

Laser Diode Pulse Driver

A laser is a device that emits light through a process of optical amplification based on the stimulated emission of electromagnetic radiation. It can have many applications in different fields like communications systems, sensorization equipment, marking and cutting of materials, 3D printing, and many others. The Laser converts electrical power into optical power, and it is the aim of this project to study pulse modulation techniques, test existing pulse drivers and propose and design electronics for a pulse driver. It's important to understand how Lasers work, their characteristics and limitations, as well as different technics and different concepts of drivers. Another challenge proposed by the company was to use free software for the design and simulation of circuits as well as for the design of the PCB, being the gEDA tools for the schematic and the PCB and Ngspice for the simulation

A LINEARIZATION METHOD FOR A UWB VCO-BASED CHIRP GENERATOR USING DUAL COMPENSATION

Ultra-Wideband (UWB) chirp generators are used on Frequency Modulated Continuous Wave (FMCW) radar systems for high-resolution and high-accuracy range measurements. At the Center for Remote Sensing of Ice Sheets (CReSIS), we have developed two UWB radar sensors for high resolution measurements of surface elevation and snow cover over Greenland and Antarctica. These radar systems are routinely operated from both surface and airborne platforms. Low cost implementations of UWB chirp generators are possible using an UWB Voltage Controlled Oscillator (VCO). VCOs possess several advantages over other competing technologies, but their frequency-voltage tuning characteristics are inherently non-linear. This nonlinear relationship between the tuning voltage and the output frequency should be corrected with a linearization system to implement a linear frequency modulated (LFM) waveform, also known as a chirp. If the waveform is not properly linearized, undesired additional frequency modulation is found in the waveform. This additional frequency modulation results in undesired sidebands at the frequency spectrum of the Intermediate Frequency (IF) stage of the FMCW radar. Since the spectrum of the filtered IF stage represents the measured range, the uncorrected nonlinear behavior of the VCO will cause a degradation of the range sensing performance of a FMCW radar. This issue is intensified as the chirp rate and nominal range of the target increase. A linearization method has been developed to linearize the output of a VCO-based chirp generator with 6 GHz of bandwidth. The linearization system is composed of a Phase Lock Loop (PLL) and an external compensation added to the loop. The nonlinear behavior of the VCO was treated as added disturbances to the loop, and a wide loop bandwidth PLL was designed for wideband compensation of these disturbances. Moreover, the PLL requires a loop filter able to attenuate the reference spurs. The PLL has been designed with a loop bandwidth as wide as possible while maintaining the reference spur level below 35 dBc. Several design considerations were made for the large loop bandwidth design. Furthermore, the large variations in the tuning sensitivity of the oscillator forced a design with a large phase margin at the average tuning sensitivity. This design constraint degraded the tracking performance of the PLL. A second compensation signal, externally generated, was added to the compensation signal of the PLL. By adding a compensation signal, which was not affected by the frequency response effects of the loop compensation, the loop tracking error is reduced. This technique enabled us to produce an output chirp signal that is a much closer replica of the scaled version of the reference signal. Furthermore, a type 1 PLL was chosen for improved transient response, compared to that of the type 2 PLL. This type of PLL requires an external compensation to obtain a finite steady state error when applying a frequency ramp to the input. The external compensation signal required to solve this issue was included in the second compensation signal mentioned above. Measurements for the PLL performance and the chirp generator performance were performed in the laboratory using a radar demonstrator. The experimental results show that the designed loop bandwidth was successfully achieved without significantly increasing the spurious signal level. The chirp generator measurements show a direct relationship between the bandwidth of the external compensation and the range resolution performance

Configurable Operational Amplifier Architectures Based on Oxide Resistive RAMs

International audienceThis paper introduces memristor-based operational amplifiers in which semiconductor resistors are suppressed and replaced by memristors. The ability of the memristive elements to hold several resistance states is exploited to design programmable closed-loop operational amplifiers. An inverting operational amplifier, an integrator and a differentiator are studied. Such designs are developed based on a calibrated memristor model, and offer dynamic configurability to realize different gains and corner frequencies at reduced chip area

Circuit techniques for low-voltage and high-speed A/D converters

The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented. It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes. An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering. The throughput of ADCs can be increased by using parallelism. This is demonstrated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.reviewe