Steady state distribution of a hyperbolic digital tanlock loop with extended pull-in range for frequency synchronization in high doppler environment

A hyperbolic arctan based Digital Tanlock Loop (D-TLL) operating with complex signals at base-band or intermediate frequencies in high Doppler environments is treated here. The arctan based loop, known as the tanlock loop (TLL), is used in software defined radio architectures for frequency acquisition and tracking. The hyperbolic nonlinearity intentionally introduced within the phase detector extends the pull-in range of the frequency for a given loop, compared to the normal D-TLL, allowing a wider frequency acquisition range which is suitable for high Doppler communications environment. In this paper we study the steady state phase noise performances of such a feedback loop for additive Gaussian noise using stochastic analysis. The stochastic model of a first-order hyperbolic loop and the theoretical analysis for the corresponding statistical distribution of the closed loop steady state phase noise are presented. The theoretical results are also verified by simulations

Digital tanlock loop architecture with no delay

This article proposes a new architecture for a digital tanlock loop which eliminates the time-delay block. The �=2 (rad) phase shift relationship between the two channels, which is generated by the delay block in the conventional timedelay digital tanlock loop (TDTL), is preserved using two quadrature sampling signals for the loop channels. The proposed system outperformed the original TDTL architecture, when both systems were tested with frequency shift keying input signal. The new system demonstrated better linearity and acquisition speed as well as improved noise performance compared with the original TDTL architecture. Furthermore, the removal of the time-delay block enables all processing to be digitally performed, which reduces the implementation complexity. Both the original TDTL and the new architecture without the delay block were modelled and simulated using ATLAB/Simulink. Implementation issues, including complexity and relation to simulation of both architectures, are also addressed

Tanlock based loop with improved performance

This thesis is focused on the design, analysis, simulation and implementation of new improved architectures of the Time Delay Digital Tanlock Loop (TDTL) based digital phase-locked loop (DPLL). The proposed architectures overcome some fundamental limitations exhibited by the original TDTL. These limitations include the presence of nonlinearity in the phase detector (PD), the non-zero phase error of the first-order loop, the restricted locking range, particularly of the second-order loop, the limited acquisition speed and the noise performance. Two approaches were adopted in this work to alleviate these limitations: the first involved modifying the original TDTL through the incorporation of auxiliary circuit blocks that enhance its performance, whilst the second involved designing new tanlock-based architectures. The proposed architectures, which resulted from the above approaches, were tested under various input signal conditions and their performance was compared with the original TDTL. The proposed architectures demonstrated an improvement of up to fourfold in terms of the acquisition times, twofold in noise performance and a marked enhancement in the linearity and in the locking range. The effectiveness of the proposed tanlock-based architectures was also assessed and demonstrated by using them in various applications, which included FM demodulation, FM threshold extension, FM demodulation with improved THD (total harmonic distortion), and Doppler effect improvement. The results from these applications showed that the performance of the new architectures outperformed the original TDTL. Real-time performance of these architectures was evaluated through implementation of some of them on an FPGA (field-programmable gate array) based system. Practical results from the prototype FPGA based implementations confirmed the simulation results obtained from MATLAB/Simulink

A nonuniform DPLL architecture for optimized performance

This paper presents the design, analysis, simulation, and implementation of the architecture of a new nonuniform-type digital phase-locked loop (DPLL). The proposed loop uses a composite phase detector (CPD), which consists of a sample-and-hold unit and an arctan block. The CPD improves the system linearity and results in a wider lock range. In addition, the loop has an adaptive controller block, which can be used to minimize the overall system sensitivity to variations in the power of the input signal. Furthermore, the controller has a tuning mechanism that gives the designer the flexibility to customize the loop parameters to suit a particular application. These performance parameters include lock range, acquisition time, phase noise or jitter, and signal-to-noise ratio enhancement. The simulation results show that the proposed loop provides flexibility to optimize the major conflicting system parameters. A prototype of the proposed system was implemented using a field-programmable gate array (FPGA), and the practical results concur with those obtained by simulation using MATLAB/Simulink. © 2013 Institute of Electrical Engineers of Japan.Published versio

A nonuniform DPLL architecture for optimized performance

This paper presents the design, analysis, simulation, and implementation of the architecture of a new nonuniform-type digital phase-locked loop (DPLL). The proposed loop uses a composite phase detector (CPD), which consists of a sample-and-hold unit and an arctan block. The CPD improves the system linearity and results in a wider lock range. In addition, the loop has an adaptive controller block, which can be used to minimize the overall system sensitivity to variations in the power of the input signal. Furthermore, the controller has a tuning mechanism that gives the designer the flexibility to customize the loop parameters to suit a particular application. These performance parameters include lock range, acquisition time, phase noise or jitter, and signal-to-noise ratio enhancement. The simulation results show that the proposed loop provides flexibility to optimize the major conflicting system parameters. A prototype of the proposed system was implemented using a field-programmable gate array (FPGA), and the practical results concur with those obtained by simulation using MATLAB/Simulink. © 2013 Institute of Electrical Engineers of Japan.Published versio

Aeronautical engineering: A continuing bibliography with indexes (supplement 304)

This bibliography lists 453 reports, articles, and other documents introduced into the NASA scientific and technical information system in May 1994. Subject coverage includes: design, construction and testing of aircraft and aircraft engines; aircraft components, equipment, and systems; ground support systems; and theoretical and applied aspects of aerodynamics and general fluid dynamics

Cumulative index to NASA Tech Briefs, 1986-1990, volumes 10-14

Tech Briefs are short announcements of new technology derived from the R&D activities of the National Aeronautics and Space Administration. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This cumulative index of Tech Briefs contains abstracts and four indexes (subject, personal author, originating center, and Tech Brief number) and covers the period 1986 to 1990. The abstract section is organized by the following subject categories: electronic components and circuits, electronic systems, physical sciences, materials, computer programs, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences

Steady State Distribution of a Hyperbolic Digital TanLock Loop with Extended Pull-in Range for Frequency Synchronization in High Doppler Environment

A hyperbolic arctan based Digital Tanlock Loop (D-TLL) operating with complex signals at base-band or intermediate frequencies in high Doppler environments is treated here. The arctan based loop, known as the tanlock loop (TLL), is used in software defined radio architectures for frequency acquisition and tracking. The hyperbolic nonlinearity intentionally introduced within the phase detector extends the pull-in range of the frequency for a given loop, compared to the normal D-TLL, allowing a wider frequency acquisition range which is suitable for high Doppler communications environment. In this paper we study the steady state phase noise performances of such a feedback loop for additive Gaussian noise using stochastic analysis. The stochastic model of a first-order hyperbolic loop and the theoretical analysis for the corresponding statistical distribution of the closed loop steady state phase noise are presented. The theoretical results are also verified by simulations

Steady State Distribution of a Hyperbolic Digital TanLock Loop with Extended Pull-in Range for Frequency Synchronization in High Doppler Environment

Thank Citatio Index Terms Digital Tanlock Loop, D-TLL, arctan, hyperbolic loop, steady state distribution, steady state phase noise, pull-in range, Frequency Synchronizatio