19 research outputs found
EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers
At nanometer manufacturing technology nodes, process variations significantly
affect circuit performance. To combat them, post- silicon clock tuning buffers
can be deployed to balance timing bud- gets of critical paths for each
individual chip after manufacturing. The challenge of this method is that path
delays should be mea- sured for each chip to configure the tuning buffers
properly. Current methods for this delay measurement rely on path-wise
frequency stepping. This strategy, however, requires too much time from ex-
pensive testers. In this paper, we propose an efficient delay test framework
(EffiTest) to solve the post-silicon testing problem by aligning path delays
using the already-existing tuning buffers in the circuit. In addition, we only
test representative paths and the delays of other paths are estimated by
statistical delay prediction. Exper- imental results demonstrate that the
proposed method can reduce the number of frequency stepping iterations by more
than 94% with only a slight yield loss.Comment: ACM/IEEE Design Automation Conference (DAC), June 201
Calculation of Generalized Polynomial-Chaos Basis Functions and Gauss Quadrature Rules in Hierarchical Uncertainty Quantification
Stochastic spectral methods are efficient techniques for uncertainty
quantification. Recently they have shown excellent performance in the
statistical analysis of integrated circuits. In stochastic spectral methods,
one needs to determine a set of orthonormal polynomials and a proper numerical
quadrature rule. The former are used as the basis functions in a generalized
polynomial chaos expansion. The latter is used to compute the integrals
involved in stochastic spectral methods. Obtaining such information requires
knowing the density function of the random input {\it a-priori}. However,
individual system components are often described by surrogate models rather
than density functions. In order to apply stochastic spectral methods in
hierarchical uncertainty quantification, we first propose to construct
physically consistent closed-form density functions by two monotone
interpolation schemes. Then, by exploiting the special forms of the obtained
density functions, we determine the generalized polynomial-chaos basis
functions and the Gauss quadrature rules that are required by a stochastic
spectral simulator. The effectiveness of our proposed algorithm is verified by
both synthetic and practical circuit examples.Comment: Published by IEEE Trans CAD in May 201
Statistical timing analysis via modern optimization lens
We formulate statistical static timing analysis (SSTA) as a mixed-integer
program and as a geometric program, utilizing histogram approximations of the
random variables involved. The geometric-programming approach scales linearly
with the number of gates and quadratically with the number of bins in the
histogram. This translates, for example, to solving the SSTA for a circuit of
400 gates with 30 bins per each histogram approximation of a random variable in
440 seconds.Comment: 23 pages, 7 figure
Reliability Modeling and Analysis of Clockless Wave Pipeline Core for Embedded Combinational Logic Design
This paper presents a model for analyzing the reliability of a clockless wave pipeline as an intellectual property (IP) core for embedded design. This design requires different clocking requirements by each embedded IP core during integration. Therefore, either partial or global lack of synchronization of the embedded clocking is considered for the data flow. The clockless wave pipeline represents an alternative to a traditional pipeline scheme; it requires an innovative computing model that is readily suitable for high-throughput computing by heterogeneous IP logic cores embedded in system-on-chip (SoC). A clockless wave pipeline technique relies on local asynchronous operation for seamless integration of a combinational core into an SoC. The basic computational components of a clockless wave pipeline are the datawaves, together with the request signals and switches. The coordination of the processing of the datawaves throughout the pipeline by the request signals is accomplished with no intermediate access in the clock control. Furthermore, the reliability of clockless-wave-pipeline-based cores is of importance when designing a reliable SOC. In this paper, the reliability in the clockless operations of the wave pipeline is analyzed by considering the datawaves and the request signals. The effect of the so-called out-of-orchestration between the datawaves and the request signals (which is referred to as a datawave fault) is proposed in the reliability analysis. A clockless-induced datawave fault model is proposed for clockless fault-tolerant design
Statistical static timing analysis considering the impact of power supply noise in VLSI circuits
As semiconductor technology is scaled and voltage level is reduced, the impact
of the variation in power supply has become very significant in predicting the realistic
worst-case delays in integrated circuits. The analysis of power supply noise is inevitable
because high correlations exist between supply voltage and delay. Supply noise analysis
has often used a vector-based timing analysis approach. Finding a set of test vectors in
vector-based approaches, however, is very expensive, particularly during the design
phase, and becomes intractable for larger circuits in DSM technology.
In this work, two novel vectorless approaches are described such that increases
in circuit delay, because of power supply noise, can be efficiently, quickly estimated.
Experimental results on ISCAS89 circuits reveal the accuracy and efficiency of my
approaches: in s38417 benchmark circuits, errors on circuit delay distributions are less
than 2%, and both of my approaches are 67 times faster than the traditional vector-based
approach. Also, the results show the importance of considering care-bits, which sensitize
the longest paths during the power supply noise analysis
Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits
Adaptive circuit design is a power-efficient approach to handle variations. Compared to conventional circuits, its implementation is more complicated especially when we deal with the fine-grained adaptivity. The unconventional and sophisticated nature of adaptive design further requires timing verification to validate the design. However timing analysis becomes more complicated due to complexities arising from nanometer VLSI technologies. A well-known challenge is process variations, which need to be addressed in timing analysis at least by considering different process corners. Adaptive circuit design further needs statistical static timing analysis (SSTA), which is much more time consuming than variation-oblivious timing analysis. Besides timing analysis, gate implementation selections of the adaptive design process are also computational expensive. This research focuses on parallel acceleration techniques for timing analysis and optimization of adaptive circuit. General purpose graphic processing units (GPGPU) and multithreading techniques are used in this work. Previous works on GPU acceleration for SSTA are mostly based on Monte Carlo based SSTA. By contrast, the parallelization techniques for principle component analysis (PCA) based SSTA are explored in this work, which is intrinsically more efficient.
We develop a batch-based scheduling algorithm to partition the circuit graph into topological levels for GPU processing and investigate other techniques such as latency hiding. We propose a multithreading based acceleration method for the process of gate implementation selection and use the same batch-based scheduling result. The experiment result shows effectiveness of our parallel acceleration for timing analysis and for optimization with the performance up to 130× and 5× speedup respectively
Least squares approximation to the distribution of project completion times with Gaussian uncertainty
This paper is motivated by the following question: How to construct good approximation for the distribution of the solution value to linear optimization problem when the random objective coefficients follow a multivariate normal distribution? Using Stein’s Identity, we show that the least squares normal approximation of the random optimal value can be computed by estimating the persistency values of the corresponding optimization problem. We further extend our method to construct a least squares quadratic estimator to improve the accuracy of the approximation; in particular, to capture the skewness of the objective. Computational studies show that the new approach provides more accurate estimates of the distributions of project completion times compared to existing methods. </jats:p