An Electromigration and Thermal Model of Power Wires for a Priori High-Level Reliability Prediction

In this paper, a simple power-distribution electrothermal model including the interconnect self-heating is used together with a statistical model of average and rms currents of functional blocks and a high-level model of fanout distribution and interconnect wirelength. Following the 2001 SIA roadmap projections, we are able to predict a priori that the minimum width that satisfies the electromigration constraints does not scale like the minimum metal pitch in future technology nodes. As a consequence, the percentage of chip area covered by power lines is expected to increase at the expense of wiring resources unless proper countermeasures are taken. Some possible solutions are proposed in the paper

Statistical Power Supply Dynamic Noise Prediction in Hierarchical Power Grid and Package Networks

One of the most crucial high performance systems-on-chip design challenge is to front their power supply noise sufferance due to high frequencies, huge number of functional blocks and technology scaling down. Marking a difference from traditional post physical-design static voltage drop analysis, /a priori dynamic voltage drop/evaluation is the focus of this work. It takes into account transient currents and on-chip and package /RLC/ parasitics while exploring the power grid design solution space: Design countermeasures can be thus early defined and long post physical-design verification cycles can be shortened. As shown by an extensive set of results, a carefully extracted and modular grid library assures realistic evaluation of parasitics impact on noise and facilitates the power network construction; furthermore statistical analysis guarantees a correct current envelope evaluation and Spice simulations endorse reliable result

Characterisation and macro-modeling of patterned micronic and nano-scale dummy metal-fills in integrated circuits

In this paper, a wideband characterization and macro-modeling of patterned micronic and nano-scale dummy metal-fills is presented. Impacts of patterned dummy metal-fill topologies including square, cross, vertical and horizontal shaped arrays on electrical performances (isolation/coupling, attenuation, guiding properties, etc…) are investigated. The validity of the proposed macro-modeling methodology is demonstrated by comparison with high frequency measurements of dedicated carrier structures including on-chip interconnects and RF inductive loops. An original extraction approach, based on local ground concept, is proposed to capture high frequency behaviour of dummy metal-fill in physics-based compact broadband SPICE model. The RLC parameters are accurately derived using fully scalable closed-form semi-analytical expressions

Electromigration modeling and layout optimization for advanced VLSI

textElectromigration (EM) is a critical problem for interconnect reliability in advanced VLSI design. Because EM is a strong function of current density, a smaller cross-sectional area of interconnects can degrade the EM-related lifetime of IC, which is expected to become more severe in future technology nodes. Moreover, as EM is governed by various factors such as temperature, material property, geometrical shape, and mechanical stress, different interconnect structures can have distinct EM issues and solutions to mitigate them. For example, one of the most prominent technologies, die stacking technology of three-dimensional (3D) ICs, can have different EM problems from that of planer ICs, due to their unique interconnects such as through-silicon vias (TSVs). This dissertation investigates EM in various interconnect structures, and applies the EM models to optimize IC layout. First, modeling of EM is developed for chip-level interconnects, such as wires, local vias, TSVs, and multi-scale vias (MSVs). Based on the models, fast and accurate EM-prediction methods are proposed for the chip-level designs. After that, by utilizing the EM-prediction methods, the layout optimization methods are suggested, such as EM-aware routing for 3D ICs and EM-aware redundant via insertion for the future technology nodes in VLSI. Experimental results show that the proposed EM modeling approaches enable fast and accurate EM evaluation for chip design, and the EM-aware layout optimization methods improve EM-robustness of advanced VLSI designs.Electrical and Computer Engineerin

A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects

A new methodology for system-on-chip-level logic-IP-internal electromigration verification is presented in this paper, which significantly improves accuracy by comprehending the impact of the parasitic RC loading and voltage-dependent pin capacitance in the library model. It additionally provides an on-the-fly retargeting capability for reliability constraints by allowing arbitrary specifications of lifetimes, temperatures, voltages, and failure rates, as well as interoperability of the IPs across foundries. The characterization part of the methodology is expedited through the intelligent IP-response modeling. The ultimate benefit of the proposed approach is demonstrated on a 28-nm design by providing an on-the-fly specification of retargeted reliability constraints. The results show a high correlation with SPICE and were obtained with an order of magnitude reduction in the verification runtime.Peer ReviewedPostprint (author's final draft

Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach

Secara tradisinya, “Field Programmable Gate Array” (FPGA) “Address Register” (AR) direka menggunakan “full custom”. Dengan keadaan geometri yang mengecut pada awal proses nod, maka keperluan untuk menimbang semula pendekatan reka bentuk yang digunakan untuk mereka bentuk FPGA AR diperlukan kerana kitaran reka bentuk meningkat dan merumitkan yang membawa kepada masa lelaran lanjut ke atas penutupan masa blok. Terdapat pelbagai jenis cabaran yang terpaksa dihadapi dalam proses 28nm dan seterusnya sekiranya pendekatan “full custom” masih digunakan untuk merekabentuk FPGA AR. Oleh itu, pendekatan berasaskan sel piawai digunakan untuk reka bentuk FPGA AR. Kitaran reka bentuk FPGA AR dapat dikurangkan dari bulan ke minggu dengan penggunaan kaedah sel piawai. Selain itu, penutupan masa dapat mengawal senario masa yang lebih. Keputusan menunjukkan bahawa FPGA AR menggunakan pendekatan berasaskan sel piawai adalah memenuhi spesifikasi reka bentuk yang diberikan. Di samping itu, jatuhan IR untuk kuasa dan bumi adalah di bawah 2mV, frekuensi adalah 330 MHz dan keluasan kawasan adalah 0.975mm2. Sebagai kesimpulan, pendekatan berasaskan sel piawai memberi pereka lebih banyak masa untuk menyelesaikan isu yang berkaitan dengan rekabentuk. Di samping itu, perubahan yang disebabkan oleh proses, voltan dan suhu dapat diperbaiki melalui kaedah pelbagai sudut dan senario ke atas FPGA AR. ________________________________________________________________________________________________________________________ Traditionally, Field Programmable Gate Array (FPGA) Address Register (AR) is designed using full custom approach. With geometries shrink on advance process node, there is a need to reconsider the design approach used to design FPGA AR because of increased design cycle and complexity that lead to more iteration time on closing block timing. Significant design effort and challenges are required in 28nm and beyond when using full custom approach. Therefore, standard cell based approach is used to design the FPGA AR. Design cycle of FPGA AR is reduced from months to weeks with the automated standard cell based approach. Besides that, timing closure is able to cover more timing scenarios. Results show that FPGA AR using standard cell based approach is meeting the given design specification. IR drop on both power and ground is achieving less than 2mV per rail, frequency of 330MHz is obtained on FPGA AR and area size is 0.975mm2. In summary, standard cell based approach gives designer more time to focus on resolving design issues, and close the design in more timing scenarios which cover more design corners to improve variation due to process, voltage and temperature

Electrical modelling of temperature distributions in on-chip interconnects, packaging, and 3D integration

Proceedings of the International Symposium on Health Informatics and Bioinformatics, 2010, p. 625-628In this talk, we will introduce a novel methodology using existing electromagnetic modelling tools for interconnect and packaging structures to simulate and model the temperature distribution without major modifications to these tools or simulated structures. This methodology can easily be integrated with the chip technology information and frame an electrical circuit simulator into an automatic, template-based simulation and optimization flow. A new accurate closed-form thermal model is further developed to simplify unnecessary object details. The model allows an equivalent medium with effective thermal conductivity (isotropic or anisotropic) to replace details in non-critical regions accurately so that complex interconnect structures can be simulated at a system level. Using these techniques, we demonstrate the modelling capability of very complex on-chip interconnects, packaging, and 3D integration technologies. © 2010 IEEE.published_or_final_versio

Simulation for Reliability, Hardware Security, and Ising Computing in VLSI Chip Design

The continued scaling of VLSI circuits has provided a wealth of opportunities andchallenges to the VLSI circuit design area. Both these challenges and opportunities, however,require new simulation tools that can enable their solution or exploitation as classicalmethods typically dealt with problem domains with smaller scales or less complexity. Inthis dissertation, simulation methods are presented to address the emerging VLSI designtopics of Electromigration induced aging and Ising computing and are then applied to theapplication areas of hardware security and graph partitioning respectively.The Electromigration aging effect in VLSI circuits is a long-term reliability issueaffecting current carrying metal wires leading to IR drop degradation. Typically, simpleanalytical equations can determine a wire’s effective age or if it will be affected by the EMaging effect at all. However, these classical methods are overly conservative and can lead toover design or unnecessary design iterations. Furthermore, it is expected that the EM agingeffect will become more severe in future Integrated Cirucits (ICs) due to increasing currentdensities and the prevalance of polycrystaline copper atom structures seen at small wiredimensions. For this reason, more comprehensive simulation techniques that can efficientlysimulate the EM effect with less conservative results can help mitigate overdesign andincrease design margins while reducing design iterations.The area of Hardware Security is becoming increasingly important as the chipsupply chain becomes more globalized and the integrity of chips becomes more diffiuclt toverify. Utilizing the accurate simulation techniques for EM, we can utilize this reliabilityeffect to demonstrate how a reliability based attack could be perpatrated. Furthermore, wecan utilize this aging effect as a defense mechanism to help us validate the integrity of anIC and detect counterfeit chips in the component supply chain market.Ising computing is an emerging method of solving combinatorial optimization problemsby simulating the interactions of so-called spin glasses and their interactions. Borrowingconcepts from quantum computing, this methods mimics the quantum interaction betweenspin glasses in such a way that finding a ground state of these spin glass models leadsto the solution of a particular problem. In this dissertation, effective methods of simulatingthe spin glass interactions using General Purpose Graphics Processing Units (GPGPUs)and finding their ground state are developed.In addition to the GPU based Ising model simulations, important combinatorialproblems can be mapped to the Ising model. In this dissertation the Ising solver is appliedto graph partitioning which can be utilized in VLSI design and many other domains as well.Specifically, solvers for the maxcut problem and the balanced min-cut partitioning problemare developed