Design methodology for a maximum sequence length MASH digital delta-sigma modulator

The paper proposes a novel structure for a MASH digital delta-sigma modulator (DDSM) in order to achieve a long sequence length. The expression for the sequence length is derived. The condition to produce the maximum sequence length is also stated. It is proved that the modulator output only depends on the structure of the first-order error feedback modulator (EFM1) which is the first stage of a Multi-stAge noise SHaping (MASH) modulator

New strategies for low noise, agile PLL frequency synthesis

Phase-Locked Loop based frequency synthesis is an essential technique employed in wireless communication systems for local oscillator generation. The ultimate goal in any design of frequency synthesisers is to generate precise and stable output frequencies with fast switching and minimal spurious and phase noise. The conflict between high resolution and fast switching leads to two separate integer synthesisers to satisfy critical system requirements. This thesis concerns a new sigma-delta fractional-N synthesiser design which is able to be directly modulated at high data rates while simultaneously achieving good noise performance. Measured results from a prototype indicate that fast switching, low noise and spurious free spectra are achieved for most covered frequencies. The phase noise of the unmodulated synthesiser was measured −113 dBc/Hz at 100 kHz offset from the carrier. The intermodulation effect in synthesisers is capable of producing a family of spurious components of identical form to fractional spurs caused in quantisation process. This effect directly introduces high spurs on some channels of the synthesiser output. Numerical and analytic results describing this effect are presented and amplitude and distribution of the resulting fractional spurs are predicted and validated against simulated and measured results. Finally an experimental arrangement, based on a phase compensation technique, is presented demonstrating significant suppression of intermodulation-borne spurs. A new technique, pre-distortion noise shaping, is proposed to dramatically reduce the impact of fractional spurs in fractional-N synthesisers. The key innovation is the introduction in the bitstream generation process of carefully-chosen set of components at identical offset frequencies and amplitudes and in anti-phase with the principal fractional spurs. These signals are used to modify the Σ-Δ noise shaping, so that fractional spurs are effectively cancelled. This approach can be highly effective in improving spectral purity and reduction of spurious components caused by the Σ-Δ modulator, quantisation noise, intermodulation effects and any other circuit factors. The spur cancellation is achieved in the digital part of the synthesiser without introducing additional circuitry. This technique has been convincingly demonstrated by simulated and experimental results

Prediction of phase noise and spurs in a nonlinear fractional-N frequency synthesizer

Integer boundary spurs appear in the passband of the loop response of fractional-N phase lock loops and are, therefore, a potentially significant component of the phase noise. In spite of measures guaranteeing spur-free modulator outputs, the interaction of the modulation noise from a divider controller with inevitable loop nonlinearities produces such spurs. This paper presents analytical predictions of the locations and amplitudes of the spurs and accompanying noise floor levels produced by interaction between a divider controller output and a PLL loop with a static nonlinearity. A key finding is that the spur locations and amplitudes can be estimated by using only the knowledge of the structure and pdf of the accumulated modulator noise and the nonlinearity. These predictions also offer new insights into why the spurs appear

An Overview of Charge Pump for Phase Lock Loop System for High Frequency Application.

Phase lock loop is fundamental buliding block of modern communication system. Phase lock loop are typically used to provide local oscillator function in radio reciver or transmitter. The design methodology and test result of charge pump structure for phase lock loop application are presented. The structure is composed to two charge/ discharge block. This paper provides study of various charge pump and discuss the technology that is used to design charge pump

Architectures for maximum-sequence-length digital delta-sigma modulators

In this paper, we extend the idea developed in some of our earlier works of using output feedback to make the quantization step in a digital delta-sigma modulator (DDSM) appear prime. This maximizes the cycle lengths for constant inputs, spreading the quantization error over the maximum number of frequency terms, and consequently, minimizing the power per tone. We show how this concept can be applied to multibit higher order error-feedback modulators (EFMs). In addition, we show that the idea can be implemented in a class of single-quantizer DDSMs (SQ-DDSM) where STF (z) = z(-L) and NTF (z) = (1 - Z(-1))(L)

High-speed nested cascaded MASH Digital Delta-Sigma Modulator-based divider controller

The MASH Digital Delta-Sigma Modulator (DDSM) based divider controller represents a speed bottleneck in state of the art commercial PLL-based fractional-N frequency synthesizers. As next generation systems require higher phase detector frequencies, there is a need to make ever faster divider controllers. This paper describes a fine-grained nested cascaded MASH DDSM which is significantly faster than state of the art divider controllers, thereby eliminating the current speed bottleneck