12,491 research outputs found
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems
A 5-layer neuromorphic vision processor whose components
communicate spike events asychronously using the address-eventrepresentation
(AER) is demonstrated. The system includes a retina
chip, two convolution chips, a 2D winner-take-all chip, a delay line
chip, a learning classifier chip, and a set of PCBs for computer
interfacing and address space remappings. The components use a
mixture of analog and digital computation and will learn to classify
trajectories of a moving object. A complete experimental setup and
measurements results are shown.Unión Europea IST-2001-34124 (CAVIAR)Ministerio de Ciencia y Tecnología TIC-2003-08164-C0
Embedding Multi-Task Address-Event- Representation Computation
Address-Event-Representation, AER, is a communication protocol that is
intended to transfer neuronal spikes between bioinspired chips. There are
several AER tools to help to develop and test AER based systems, which may
consist of a hierarchical structure with several chips that transmit spikes
among them in real-time, while performing some processing. Although these
tools reach very high bandwidth at the AER communication level, they require
the use of a personal computer to allow the higher level processing of the
event information. We propose the use of an embedded platform based on a
multi-task operating system to allow both, the AER communication and
processing without the requirement of either a laptop or a computer. In this
paper, we present and study the performance of an embedded multi-task AER
tool, connecting and programming it for processing Address-Event
information from a spiking generator.Ministerio de Ciencia e Innovación TEC2006-11730-C03-0
Spike Processing on an Embedded Multi-task Computer: Image Reconstruction
There is an emerging philosophy, called Neuro-informatics, contained
in the Artificial Intelligence field, that aims to emulate how living beings do tasks
such as taking a decision based on the interpretation of an image by emulating spiking
neurons into VLSI designs and, therefore, trying to re-create the human brain at
its highest level. Address-Event-Representation (AER) is a communication protocol
that has embedded part of the processing. It is intended to transfer spikes between
bioinspired chips. An AER based system may consist of a hierarchical structure with
several chips that transmit spikes among them in real-time, while performing some
processing. There are several AER tools to help to develop and test AER based systems.
These tools require the use of a computer to allow the higher level processing of
the event information, reaching very high bandwidth at the AER communication level.
We propose the use of an embedded platform based on a multi-task operating system
to allow both, the AER communication and processing without the requirement of either
a laptop or a computer. In this paper, we present and study the performance of a
new philosophy of a frame-grabber AER tool based on a multi-task environment. This
embedded platform is based on the Intel XScale processor which is governed by an
embedded GNU/Linux system. We have connected and programmed it for processing
Address-Event information from a spiking generator.Ministerio de Educación y Ciencia TEC2006-11730-C03-0
Tuning a binary ferromagnet into a multi-state synapse with spin-orbit torque induced plasticity
Inspired by ion-dominated synaptic plasticity in human brain, artificial
synapses for neuromorphic computing adopt charge-related quantities as their
weights. Despite the existing charge derived synaptic emulations, schemes of
controlling electron spins in ferromagnetic devices have also attracted
considerable interest due to their advantages of low energy consumption,
unlimited endurance, and favorable CMOS compatibility. However, a generally
applicable method of tuning a binary ferromagnet into a multi-state memory with
pure spin-dominated synaptic plasticity in the absence of an external magnetic
field is still missing. Here, we show how synaptic plasticity of a
perpendicular ferromagnetic FM1 layer can be obtained when it is
interlayer-exchange-coupled by another in-plane ferromagnetic FM2 layer, where
a magnetic-field-free current-driven multi-state magnetization switching of FM1
in the Pt/FM1/Ta/FM2 structure is induced by spin-orbit torque. We use current
pulses to set the perpendicular magnetization state which acts as the synapse
weight, and demonstrate spintronic implementation of the excitatory/inhibitory
postsynaptic potentials and spike timing-dependent plasticity. This
functionality is made possible by the action of the in-plane interlayer
exchange coupling field which leads to broadened, multi-state magnetic reversal
characteristics. Numerical simulations, combined with investigations of a
reference sample with a single perpendicular magnetized Pt/FM1/Ta structure,
reveal that the broadening is due to the in-plane field component tuning the
efficiency of the spin-orbit-torque to drive domain walls across a landscape of
varying pinning potentials. The conventionally binary FM1 inside our
Pt/FM1/Ta/FM2 structure with inherent in-plane coupling field is therefore
tuned into a multi-state perpendicular ferromagnet and represents a synaptic
emulator for neuromorphic computing.Comment: 37 pages with 11 figures, including 20 pages for manuscript and 17
pages for supplementary informatio
Memory and information processing in neuromorphic systems
A striking difference between brain-inspired neuromorphic processors and
current von Neumann processors architectures is the way in which memory and
processing is organized. As Information and Communication Technologies continue
to address the need for increased computational power through the increase of
cores within a digital processor, neuromorphic engineers and scientists can
complement this need by building processor architectures where memory is
distributed with the processing. In this paper we present a survey of
brain-inspired processor architectures that support models of cortical networks
and deep neural networks. These architectures range from serial clocked
implementations of multi-neuron systems to massively parallel asynchronous ones
and from purely digital systems to mixed analog/digital systems which implement
more biological-like models of neurons and synapses together with a suite of
adaptation and learning mechanisms analogous to the ones found in biological
nervous systems. We describe the advantages of the different approaches being
pursued and present the challenges that need to be addressed for building
artificial neural processing systems that can display the richness of behaviors
seen in biological systems.Comment: Submitted to Proceedings of IEEE, review of recently proposed
neuromorphic computing platforms and system
Scaling of a large-scale simulation of synchronous slow-wave and asynchronous awake-like activity of a cortical model with long-range interconnections
Cortical synapse organization supports a range of dynamic states on multiple
spatial and temporal scales, from synchronous slow wave activity (SWA),
characteristic of deep sleep or anesthesia, to fluctuating, asynchronous
activity during wakefulness (AW). Such dynamic diversity poses a challenge for
producing efficient large-scale simulations that embody realistic metaphors of
short- and long-range synaptic connectivity. In fact, during SWA and AW
different spatial extents of the cortical tissue are active in a given timespan
and at different firing rates, which implies a wide variety of loads of local
computation and communication. A balanced evaluation of simulation performance
and robustness should therefore include tests of a variety of cortical dynamic
states. Here, we demonstrate performance scaling of our proprietary Distributed
and Plastic Spiking Neural Networks (DPSNN) simulation engine in both SWA and
AW for bidimensional grids of neural populations, which reflects the modular
organization of the cortex. We explored networks up to 192x192 modules, each
composed of 1250 integrate-and-fire neurons with spike-frequency adaptation,
and exponentially decaying inter-modular synaptic connectivity with varying
spatial decay constant. For the largest networks the total number of synapses
was over 70 billion. The execution platform included up to 64 dual-socket
nodes, each socket mounting 8 Intel Xeon Haswell processor cores @ 2.40GHz
clock rates. Network initialization time, memory usage, and execution time
showed good scaling performances from 1 to 1024 processes, implemented using
the standard Message Passing Interface (MPI) protocol. We achieved simulation
speeds of between 2.3x10^9 and 4.1x10^9 synaptic events per second for both
cortical states in the explored range of inter-modular interconnections.Comment: 22 pages, 9 figures, 4 table
Highly Scalable Neuromorphic Hardware with 1-bit Stochastic nano-Synapses
Thermodynamic-driven filament formation in redox-based resistive memory and
the impact of thermal fluctuations on switching probability of emerging
magnetic switches are probabilistic phenomena in nature, and thus, processes of
binary switching in these nonvolatile memories are stochastic and vary from
switching cycle-to-switching cycle, in the same device, and from
device-to-device, hence, they provide a rich in-situ spatiotemporal stochastic
characteristic. This work presents a highly scalable neuromorphic hardware
based on crossbar array of 1-bit resistive crosspoints as distributed
stochastic synapses. The network shows a robust performance in emulating
selectivity of synaptic potentials in neurons of primary visual cortex to the
orientation of a visual image. The proposed model could be configured to accept
a wide range of nanodevices.Comment: 9 pages, 6 figure
MorphIC: A 65-nm 738k-Synapse/mm Quad-Core Binary-Weight Digital Neuromorphic Processor with Stochastic Spike-Driven Online Learning
Recent trends in the field of neural network accelerators investigate weight
quantization as a means to increase the resource- and power-efficiency of
hardware devices. As full on-chip weight storage is necessary to avoid the high
energy cost of off-chip memory accesses, memory reduction requirements for
weight storage pushed toward the use of binary weights, which were demonstrated
to have a limited accuracy reduction on many applications when
quantization-aware training techniques are used. In parallel, spiking neural
network (SNN) architectures are explored to further reduce power when
processing sparse event-based data streams, while on-chip spike-based online
learning appears as a key feature for applications constrained in power and
resources during the training phase. However, designing power- and
area-efficient spiking neural networks still requires the development of
specific techniques in order to leverage on-chip online learning on binary
weights without compromising the synapse density. In this work, we demonstrate
MorphIC, a quad-core binary-weight digital neuromorphic processor embedding a
stochastic version of the spike-driven synaptic plasticity (S-SDSP) learning
rule and a hierarchical routing fabric for large-scale chip interconnection.
The MorphIC SNN processor embeds a total of 2k leaky integrate-and-fire (LIF)
neurons and more than two million plastic synapses for an active silicon area
of 2.86mm in 65nm CMOS, achieving a high density of 738k synapses/mm.
MorphIC demonstrates an order-of-magnitude improvement in the area-accuracy
tradeoff on the MNIST classification task compared to previously-proposed SNNs,
while having no penalty in the energy-accuracy tradeoff.Comment: This document is the paper as accepted for publication in the IEEE
Transactions on Biomedical Circuits and Systems journal (2019), the
fully-edited paper is available at
https://ieeexplore.ieee.org/document/876400
Scaling of a large-scale simulation of synchronous slow-wave and asynchronous awake-like activity of a cortical model with long-range interconnections
Cortical synapse organization supports a range of dynamic states on multiple
spatial and temporal scales, from synchronous slow wave activity (SWA),
characteristic of deep sleep or anesthesia, to fluctuating, asynchronous
activity during wakefulness (AW). Such dynamic diversity poses a challenge for
producing efficient large-scale simulations that embody realistic metaphors of
short- and long-range synaptic connectivity. In fact, during SWA and AW
different spatial extents of the cortical tissue are active in a given timespan
and at different firing rates, which implies a wide variety of loads of local
computation and communication. A balanced evaluation of simulation performance
and robustness should therefore include tests of a variety of cortical dynamic
states. Here, we demonstrate performance scaling of our proprietary Distributed
and Plastic Spiking Neural Networks (DPSNN) simulation engine in both SWA and
AW for bidimensional grids of neural populations, which reflects the modular
organization of the cortex. We explored networks up to 192x192 modules, each
composed of 1250 integrate-and-fire neurons with spike-frequency adaptation,
and exponentially decaying inter-modular synaptic connectivity with varying
spatial decay constant. For the largest networks the total number of synapses
was over 70 billion. The execution platform included up to 64 dual-socket
nodes, each socket mounting 8 Intel Xeon Haswell processor cores @ 2.40GHz
clock rates. Network initialization time, memory usage, and execution time
showed good scaling performances from 1 to 1024 processes, implemented using
the standard Message Passing Interface (MPI) protocol. We achieved simulation
speeds of between 2.3x10^9 and 4.1x10^9 synaptic events per second for both
cortical states in the explored range of inter-modular interconnections.Comment: 22 pages, 9 figures, 4 table
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