Error control for reliable digital data transmission and storage systems

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this paper we present some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative alorithm to find the error locator polynomial. Two codes are considered: (1) a d sub min = 4 single-byte-error-correcting (SBEC), double-byte-error-detecting (DBED) RS code; and (2) a d sub min = 6 double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS code

Design and Analysis of an Adjacent Multi-bit Error Correcting Code for Nanoscale SRAMs

Increasing static random access memory (SRAM) bitcell density is a major driving force for semiconductor technology scaling. The industry standard 2x reduction in SRAM bitcell area per technology node has lead to a proliferation in memory intensive applications as greater memory system capacity can be realized per unit area. Coupled with this increasing capacity is an increasing SRAM system-level soft error rate (SER). Soft errors, caused by galactic radiation and radioactive chip packaging material corrupt a bitcell’s data-state and are a potential cause of catastrophic system failures. Further, reductions in device geometries, design rules, and sensitive node capacitances increase the probability of multiple adjacent bitcells being upset per particle strike to over 30% of the total SER below the 45 nm process node. Traditionally, these upsets have been addressed using a simple error correction code (ECC) combined with word interleaving. With continued scaling however, errors beyond this setup begin to emerge. Although more powerful ECCs exist, they come at an increased overhead in terms of area and latency. Additionally, interleaving adds complexity to the system and may not always be feasible for the given architecture. In this thesis, a new class of ECC targeted toward adjacent multi-bit upsets (MBU) is proposed and analyzed. These codes present a tradeoff between the currently popular single error correcting-double error detecting (SEC-DED) ECCs used in SRAMs (that are unable to correct MBUs), and the more robust multi-bit ECC schemes used for MBU reliability. The proposed codes are evaluated and compared against other ECCs using a custom test suite and multi-bit error channel model developed in Matlab as well as Verilog hardware description language (HDL) implementations synthesized using Synopsys Design Compiler and a commercial 65 nm bulk CMOS standard cell library. Simulation results show that for the same check-bit overhead as a conventional 64 data-bit SEC-DED code, the proposed scheme provides a corrected-SER approximately equal to the Bose-Chaudhuri- Hocquenghem (BCH) double error correcting (DEC) code, and a 4.38x improvement over the SEC-DED code in the same error channel. While, for 3 additional check-bits (still 3 less than the BCH DEC code), a triple adjacent error correcting version of the proposed code provides a 2.35x improvement in corrected-SER over the BCH DEC code for 90.9% less ECC circuit area and 17.4% less error correction delay. For further verification, a 0.4-1.0 V 75 kb single-cycle SRAM macro protected with a programmable, up-to-3-adjacent-bit-correcting version of the proposed ECC has been fab- ricated in a commercial 28 nm bulk CMOS process. The SRAM macro has undergone neu- tron irradiation testing at the TRIUMF Neutron Irradiation Facility in Vancouver, Canada. Measurements results show a 189x improvement in SER over an unprotected memory with no ECC enabled and a 5x improvement over a traditional single-error-correction (SEC) code at 0.5 V using 1-way interleaving for the same number of check-bits. This is compa- rable with the 4.38x improvement observed in simulation. Measurement results confirm an average active energy of 0.015 fJ/bit at 0.4 V, and average 80 mV reduction in VDDMIN across eight packaged chips by enabling the ECC. Both the SRAM macro and ECC circuit were designed for dynamic voltage and frequency scaling for both nominal and low voltage applications using a full-custom circuit design flow

Texas Register

A weekly publication, the Texas Register serves as the journal of state agency rulemaking for Texas. Information published in the Texas Register includes proposed, adopted, withdrawn and emergency rule actions, notices of state agency review of agency rules, governor's appointments, attorney general opinions, and miscellaneous documents such as requests for proposals. After adoption, these rulemaking actions are codified into the Texas Administrative Code

Texas Register

A weekly publication, the Texas Register serves as the journal of state agency rulemaking for Texas. Information published in the Texas Register includes proposed, adopted, withdrawn and emergency rule actions, notices of state agency review of agency rules, governor's appointments, attorney general opinions, and miscellaneous documents such as requests for proposals. After adoption, these rulemaking actions are codified into the Texas Administrative Code

Best Environmental Management Practice in the Fabricated Metal Product manufacturing sector

This report encloses technical information pertinent to the development of Best Environmental Management Practices (BEMPs) for the Sectoral Reference Document on the Fabricated Metal Products manufacturing sector, to be produced by the European Commission according to Article 46 of Regulation (EC) No 1221/2009 (EMAS Regulation). The BEMPs, both of technological and management nature (identified in close cooperation with a technical working group) address all the relevant environmental aspects of the Fabricated Metal Products manufacturing facilities. The BEMPs described in this report provide guidance on the cross-cutting issues and optimisation of utilities of the manufacturing facilities. Moreover, the BEMPs cover also the most relevant manufacturing processes, looking at energy and material efficiency, protecting and enhancing biodiversity, using of renewable energy and using rationally and effectively chemicals e.g. for cooling of various machining processes. Each BEMP gives a wide range of information and outlines the achieved environmental benefits, appropriate environmental performance indicators to measure environmental performance against the proposed benchmarks of excellence, economics etc. aiming at giving inspiration and guidance to any company of the sector who wishes to improve its environmental performance.JRC.B.5-Circular Economy and Industrial Leadershi

Annual report for the town of Bristol, New Hampshire fiscal year ending December 31, 2011.

This is an annual report containing vital statistics for a town/city in the state of New Hampshire

Space Shuttle program communication and tracking systems interface analysis

The Space Shuttle Program Communications and Tracking Systems Interface Analysis began April 18, 1983. During this time, the shuttle communication and tracking systems began flight testing. Two areas of analysis documented were a result of observations made during flight tests. These analyses involved the Ku-band communication system. First, there was a detailed analysis of the interface between the solar max data format and the Ku-band communication system including the TDRSS ground station. The second analysis involving the Ku-band communication system was an analysis of the frequency lock loop of the Gunn oscillator used to generate the transmit frequency. The stability of the frequency lock loop was investigated and changes to the design were reviewed to alleviate the potential loss of data due the loop losing lock and entering the reacquisition mode. Other areas of investigation were the S-band antenna analysis and RF coverage analysis

UTPA Graduate Catalog 2013-2015

https://scholarworks.utrgv.edu/edinburglegacycatalogs/1085/thumbnail.jp