Design Of Low-capacitance And High-speed Electrostatic Discharge (esd) Devices For Low-voltage Protection Applications

Electrostatic discharge (ESD) is defined as the transfer of charge between bodies at different potentials. The electrostatic discharge induced integrated circuit damages occur throughout the whole life of a product from the manufacturing, testing, shipping, handing, to end user operating stages. This is particularly true as microelectronics technology continues shrink to nano-metric dimensions. The ESD related failures is a major IC reliability concern and results in a loss of millions dollars to the semiconductor industry each year. Several ESD stress models and test methods have been developed to reproduce the real world ESD discharge events and quantify the sensitivity of ESD protection structures. The basic ESD models are: Human body model (HBM), Machine model (MM), and Charged device model (CDM). To avoid or reduce the IC failure due to ESD, the on-chip ESD protection structures and schemes have been implemented to discharge ESD current and clamp overstress voltage under different ESD stress events. Because of its simple structure and good performance, the junction diode is widely used in on-chip ESD protection applications. This is particularly true for ESD protection of lowvoltage ICs where a relatively low trigger voltage for the ESD protection device is required. However, when the diode operates under the ESD stress, its current density and temperature are far beyond the normal conditions and the device is in danger of being damaged. For the design of effective ESD protection solution, the ESD robustness and low parasitic capacitance are two major concerns. The ESD robustness is usually defined after the failure current It2 and on-state resistance Ron. The transmission line pulsing (TLP) measurement is a very effective tool for evaluating the ESD robustness of a circuit or single element. This is particularly helpful in iv characterizing the effect of HBM stress where the ESD-induced damages are more likely due to thermal failures. Two types of diodes with different anode/cathode isolation technologies will be investigated for their ESD performance: one with a LOCOS (Local Oxidation of Silicon) oxide isolation called the LOCOS-bound diode, the other with a polysilicon gate isolation called the polysilicon-bound diode. We first examine the ESD performance of the LOCOS-bound diode. The effects of different diode geometries, metal connection patterns, dimensions and junction configurations on the ESD robustness and parasitic capacitance are investigated experimentally. The devices considered are N+/P-well junction LOCOS-bound diodes having different device widths, lengths and finger numbers, but the approach applies generally to the P+/N-well junction diode as well. The results provide useful insights into optimizing the diode for robust HBM ESD protection applications. Then, the current carrying and voltage clamping capabilities of LOCOS- and polysiliconbound diodes are compared and investigated based on both TCAD simulation and experimental results. Comparison of these capabilities leads to the conclusion that the polysilicon-bound diode is more suited for ESD protection applications due to its higher performance. The effects of polysilicon-bound diode’s design parameters, including the device width, anode/cathode length, finger number, poly-gate length, terminal connection and metal topology, on the ESD robustness are studied. Two figures of merits, FOM_It2 and FOM_Ron, are developed to better assess the effects of different parameters on polysilicon-bound diode’s overall ESD performance. As latest generation package styles such as mBGAs, SOTs, SC70s, and CSPs are going to the millimeter-range dimensions, they are often effectively too small for people to handle with fingers. The recent industry data indicates the charged device model (CDM) ESD event becomes v increasingly important in today’s manufacturing environment and packaging technology. This event generates highly destructive pulses with a very short rise time and very small duration. TLP has been modified to probe CDM ESD protection effectiveness. The pulse width was reduced to the range of 1-10 ns to mimic the very fast transient of the CDM pulses. Such a very fast TLP (VFTLP) testing has been used frequently for CDM ESD characterization. The overshoot voltage and turn-on time are two key considerations for designing the CDM ESD protection devices. A relatively high overshoot voltage can cause failure of the protection devices as well as the protected devices, and a relatively long turn-on time may not switch on the protection device fast enough to effectively protect the core circuit against the CDM stress. The overshoot voltage and turn-on time of an ESD protection device can be observed and extracted from the voltage versus time waveforms measured from the VFTLP testing. Transient behaviors of polysilicon-bound diodes subject to pulses generated by the VFTLP tester are characterized for fast ESD events such as the charged device model. The effects of changing devices’ dimension parameters on the transient behaviors and on the overshoot voltage and turn-on time are studied. The correlation between the diode failure and poly-gate configuration under the VFTLP stress is also investigated. Silicon-controlled rectifier (SCR) is another widely used ESD device for protecting the I/O pins and power supply rails of integrated circuits. Multiple fingers are often needed to achieve optimal ESD protection performance, but the uniformity of finger triggering and current flow is always a concern for multi-finger SCR devices operating under the post-snapback region. Without a proper understanding of the finger turn-on mechanism, design and realization of robust SCRs for ESD protection applications are not possible. Two two-finger SCRs with different combinations of anode/cathode regions are considered, and their finger turn-on vi uniformities are analyzed based on the I-V characteristics obtained from the transmission line pulsing (TLP) tester. The dV/dt effect of pulses with different rise times on the finger turn-on behavior of the SCRs are also investigated experimentally. In this work, unless noted otherwise, all the measurements are conducted using the Barth 4002 transmission line pulsing (TLP) and Barth 4012 very-fast transmission line pulsing (VFTLP) testers

CDM Robust & Low Noise ESD protection circuits

In spite of significant progress during last couple of decades, ESD still affects production yields, manufacturing costs, product quality, product reliability and profitability. The objective of an ESD protection circuit is to create a harmless shunting path for the static electricity before it damages the sensitive electronic circuits. As the devices are scaling down, while ESD energy remains the same, VLSIs are becoming more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. Hence, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Furthermore with scaling, the integration of analog blocks such as ADC, PLL’s, DLL’s, oscillator etc. on digital chips has provided cheap system on chip (SOC) solutions. However, when analog and digital chip are combined into single mixed-signal chip, on-chip noise coupling from the digital to the analog circuitry through ESD protection circuits becomes a big concern. Thus, increasing supply noise isolation while ensuring the ESD protection robustness is also a big challenge. In this thesis, several ESD protection circuits and devices have been proposed to address the critical issues like increased leakage current, slower turn-on time of devices, increased susceptibility to power supply isolation etc. The proposed ESD protection circuits/devices have been classified into two categories: Pad based ESD protection in which the ESD protection circuits are placed in the I/O pads, and Rail based ESD in which ESD protection circuit is placed between power supplies. In our research, both these aspects have been investigated. The Silicon Controlled Rectifier (SCR) based devices have been used for Pad ESD protection as they have highest ESD protection level per unit area. Two novel devices Darlington based SCR (DSCR) and NMOS Darlington based SCR (NMOS-DSCR) having faster turn-on time, lower first breakdown voltage and low capacitance have been proposed. The transient clamps have been investigated and optimized for Rail based ESD protection. In this research, we have addressed the issue of leakage current in transient clamps. A methodology has been purposed to reduce the leakage current by more than 200,000 times without having major impact on the ESD performance. Also, the issue of noise coupling from digital supply to analog supply through the ESD protection circuits has been addressed. A new transient clamp has been proposed to increase the power supply noise isolation. Finally, a new methodology of placement of analog circuit with respect to transient clamp has been proposed to further increase the power supply noise isolation

Electrostatic Discharge Protection Device for Digital Circuits and for Applications with Input/Output Bipolar Voltage Much Higher than the Core Circuit Power Supply

An electrostatic discharge (ESD) device and method is provided. The ESD device can comprise a substrate doped to a first conductivity type, an epitaxial region doped to the second conductivity type, and a first well doped to the first conductivity type disposed in the substrate. The first well can comprise a first region doped to the first conductivity type, a second region doped to a second conductivity type, and a first isolation region disposed between the first region and the second region. The ESD device can also comprise a second well doped to a second conductivity type disposed in the substrate adjacent to the first well, where the second well can comprise a third region doped to the first conductivity type, a fourth region doped to the second conductivity type, and a second isolation region disposed between the third region and the fourth region. Still further, the ESD device can include a first trigger contact and second trigger contact comprising highly doped regions of eith

Analysis of design strategies for RF ESD problems in CMOS circuits

This thesis analyses the design strategies used to protect RF circuits that are implemented in CMOS technologies. It investigates, in detail, the physical mechanisms involved when a ggNMOS structure is exposed to an ESD event and undergoes snapback. The understanding gained is used to understand why the performance of the current RF ESD clamp is poor and suggestions are made as to how the performance of ggNMOS clamps can be improved beyond the current body of knowledge. The ultimate aim is to be able to design effective ESD protection clamps whilst minimising the effect the circuit has on RF I/O signals. A current ggNMOS based RF ESD I/O protection circuit is analysed in detail using a Transmission Line Pulse (TLP) tester. This is shown to be a very effective diagnostic tool by showing many characteristics of the ggNMOS during the triggering and conducting phase of the ESD event and demonstrate deficiencies in the clamp design. The use of a FIB enhances the analysis by allowing the isolation of individual components in the circuit and therefore their analysis using the TLP tester. SPICE simulations are used to provide further commentary on the debate surrounding the specification required of a TLP tester for there to be a good correlation between a TLP test and the industry standard Human Body Model (HBM) ESD test. Finite element simulations are used to probe deeper in to the mechanisms involved when a ggNMOS undergoes snapback especially with regard to the contribution parasitic components within the ggNMOS make to the snapback process. New ggNMOS clamps are proposed which after some modification are shown to work. Some of the finite element experiments are repeated in a 0.18μπ7. process CMOS test chip and a comparison is made between the two sets of results. In the concluding chapter understanding that has been gained from previous chapters is combined with the published body of knowledge to suggest and explain improvements in the design of a ggNMOS for RF and standard applications. These improvements will improve homogeneity of ggNMOS operation thus allowing the device size to be reduced and parasitic loading for a given ESD performance. These techniques can also be used to ensure that the ESD current does not take an unintended path through the chip

Transient Safe Operating Area (tsoa) For Esd Applications

A methodology to obtain design guidelines for gate oxide input pin protection and high voltage output pin protection in Electrostatic Discharge (ESD) time frame is developed through measurements and Technology Computer Aided Design (TCAD). A set of parameters based on transient measurements are used to define Transient Safe Operating Area (TSOA). The parameters are then used to assess effectiveness of protection devices for output and input pins. The methodology for input pins includes establishing ESD design targets under Charged Device Model (CDM) type stress in low voltage MOS inputs. The methodology for output pins includes defining ESD design targets under Human Metal Model (HMM) type stress in high voltage Laterally Diffused MOS (LDMOS) outputs. First, the assessment of standalone LDMOS robustness is performed, followed by establishment of protection design guidelines. Secondly, standalone clamp HMM robustness is evaluated and a prediction methodology for HMM type stress is developed based on standardized testing. Finally, LDMOS and protection clamp parallel protection conditions are identifie

Low-Leakage ESD Power Supply Clamps in General Purpose 65 nm CMOS Technology

Electrostatic discharge (ESD) is a well-known contributor that reduces the reliability and yield of the integrated circuits (ICs). As ICs become more complex, they are increasingly susceptible to such failures due to the scaling of physical dimensions of devices and interconnect on a chip [1]. These failures are caused by excessive electric field and/or excessive current densities and result in the dielectric breakdown, electromigration of metal lines and contacts. ESD can affect the IC in its different life stages, from wafer fabrication process to failure in the field. Furthermore, ESD events can damage the integrated circuit permanently (hard failure), or cause a latent damage (soft failure) [2]. ESD protection circuits consisting of I/O protection and ESD power supply clamps are routinely used in ICs to protect them against ESD damage. The main objective of the ESD protection circuit is to provide a low-resistive discharge path between any two pins of the chip to harmlessly discharge ESD energy without damaging the sensitive circuits. The main target of this thesis is to design ESD power supply clamps that have the lowest possible leakage current without degrading the ESD protection ability in general purpose TSMC 65 nm CMOS technology. ESD clamps should have a very low-leakage current and should be stable and immune to the power supply noise under the normal operating conditions of the circuit core. Also, the ESD clamps must be able to handle high currents under an ESD event. All designs published in the general purpose 65 nm CMOS technology have used the SCR as the clamping element since the SCR has a higher current carrying capability compared to an MOS transistor of the same area [3]. The ESD power supply clamp should provide a low-resistive path in both directions to be able to deal with both PSD and NDS zapping modes. The SCR based design does not provide the best ESD protection for the NDS zapping mode (positive ESD stress at VSS with grounded VDD node) since it has two parasitic resistances (RNwell and RPsub) and one parasitic diode (the collector to base junction diode of the PNP transistor) in the path from the VSS to VDD. Furthermore, SCR-based designs are not suitable for application that exposed to hot switching or ionizing radiation [2]. In GP process, the gate oxide thickness of core transistors is reduced compared with LP process counterpart to achieve higher performance designs for high-frequency applications using 1 V core transistors and 2.5 V I/O option. The thinner gate oxide layer results in higher leakage current due to gate tunneling [4]. Therefore, using large thin oxide MOS transistors as clamping elements will result in a huge leakage. In this thesis, four power supply ESD clamps are proposed in which thick oxide MOS transistors are used as the main clamping element. Therefore, the low-leakage current feature is achieved without significantly degrading the ESD performance. In addition, the parasitic diode of the MOS transistors provides the protection against NSD-mode. In this thesis, two different ESD power supply clamp architectures are proposed: standalone ESD power supply clamps and hybrid ESD power supply clamps. Two standalone clamps are proposed: a transient PMOS based ESD clamp with thyristor delay element (PTC), and a static diode triggered power supply (DTC). The standalone clamps were designed to protect the circuit core against ±125 V CDM stress by limiting the voltage between the two power rails to less than the oxide breakdown voltage of the core transistors, BVOXESD = 5 V. The large area of this architecture was the price for maintaining the low-leakage current and an adequate ESD protection. The hybrid clamp architecture was proposed to provide a higher ESD protection, against ±300 V CDM stress, while reducing the layout area and maintaining the low-leakage feature. In the hybrid clamp structure, two clamps are connected in parallel between the two power supply rails, a static clamp, and a transient clamp. The static clamp triggers first and starts to sink the ESD energy and then an RC network triggers the primary transient clamp to sink most of the ESD stress. Two hybrid designs were proposed: PMOS ESD power supply clamp with thyristor delay element and diodes (PTDC), and NMOS ESD power supply clamp with level shifter delay element and diode (NLDC). Simulation results show that the proposed clamps are capable of protecting the circuit core against ±1.5 kV HBM and at least against ±125 V CDM stresses. The measurement results show that all of the proposed clamps are immune against false triggering, and transient induced latch-up. Furthermore, all four designs have responded favorably to the 4 V ESD-like pulse voltage under both chip powered and not powered conditions and after the stress ends the designs turned off. Finally, TLP measurement results show that all four proposed designs meet the minimum design requirement of the ESD protection circuit in the 65 nm CMOS technology (i.e. HBM protection level of ±1.5 kV )

Organic Semiconductors-Based Devices Electrical Reliability to Environmental Stress

In this thesis, I report on the characterisation of the response of organic semiconductor based devices, namely organic light-emitting diodes (OLEDs), organic field-effect transistors (OFETs) and organic photovoltaic diodes (OPVDs) to environmental stress factors such as electrostatic discharge (ESD) and neutrons irradiation. The ESD stress was obtained by means of a transmission line-pulsing (TLP), responsible to generate current pulses with an increasing amplitude and a duration of few tens of nanoseconds. The exposure to neutron irradiation was obtained in the pulsed neutron and muon source at ISIS part of the Rutherford Appleton Laboratories (RAL). The tested devices were: P3HT (poly(3-hexylthiophene)):PCBM ([6,6]- phenyl C61 butyric acid methyl ester) bulk heterojunction solar cells; PBTTT (poly(2,5-bis(3-hexadecylthiophen-2-yl)thieno[3,2- b]thiophene) and P3HT OFETs; F8BT (poly(9,9'-dioctylfluorene-alt-benzothiadiazole)) OLEDs. An analysis of both electrical (IV and JV curves, Electroluminescence (EL)) and optical (photoluminescence (PL), Raman Spectroscopy) characteristics of tested devices prior and following the exposure to various degrees of ESD, neutron irradiation or both is reported. For each tested device I obtained the respective TLP parameters (the leakage current (ILEAK), the TLP current (ITLP), the TLP voltage (VTLP), the TLP resistance (RTLP)) and the correlation of these with parameters extracted by means of their electrical/optical characterisation, namely: (i) the charge mobility, the threshold voltage (VTH) and the on/off ratio of OFETs; (ii) the current density (Jsc), the open-circuit voltage (Voc), the fill factor (FF) and the power conversion efficiency (η) of OPVs; (iii) the turn-on voltage (Von), the external quantum efficiency (EQE) and the EL maximum wavelength emission (λmax) of OLEDs. Importantly, the activity carried out in this thesis gives novel insights about the response of conjugated polymer-based devices with respect to the stressing stimuli (ESD events, cosmic rays) they are exposed to in their most suitable application fields (space, medicine, robotics), such as the energy necessary to cause a total or partial failure during ESD events, the requirements necessary to design electrical protections, the expected loss of device figures after a decade of exposure to cosmic rays. Interestingly, the results in this thesis reported point out, in most of the cases, an excellent robustness of these devices to both ESD and cosmic rays stress. In fact, whilst technology silicon-based is found to suffer a permanent failure in most of the cases for an applied TLP power lower than 400 W, polymer-based technology was found to withstand up to 800 W (OPVs and OLEDs) without suffering permanent damages. As regards the stress correlated to the same dose of neutrons irradiation, optoelectronic devices based on inorganic semiconductors suffer of a 90% reduction of their figures of merit (JSC, h), whilst the same figures are reduced of only 20% in polymer-based devices. Although previous works are reported in literature, the work reported in this thesis, at the best of my knowledge, is the first work reporting a systematic quantitative TLP characterisation of organic devices along with a qualitative description of the effects on the organic materials within these devices because of the conditions imposed by the TLP test (high-frequency, high-voltage). Therefore, this thesis opens a new scenario proposing an investigating tool aimed both at measuring parameters useful for the design of the devices and at highlighting organic materials properties that can lead organic electronics to gain its definitive momentum

Optimization and Modelling of Semiconductor Devices in a 0.35 µm CMOS High Temperature Technology

Die vorliegende Arbeit beschäftigte sich mit der Optimierung und Modellierung von Bauelementen in einer 0,35 μm-CMOS-Technologie, die speziell für den Betrieb in einem erweiterten Temperaturbereich von −40 ℃ bis 250 ℃ vorgesehen ist. Bei dieser Technologie handelt es sich um eine Weiterentwicklung einer 1 μm-Technologie, die in weiten Teilen der Prozessierung modifiziert wurde. Durch die geringe Strukturbreite lassen sich komplexere Schaltungen und eine höhere Packungsdichte realisieren. Die Herstellung erfolgt in einer Dünnfilm-SOI-Technologie, die gegenüber einer üblicherweise verwendeten Bulk-Technologie deutliche Vorteile beim Hochtemperaturbetrieb bietet. Die zahlreichen Veränderungen in der neuen Technologie erforderten zunächst die Anpassung des elektrischen Verhaltens verschiedener Bauelemente an die gesetzten Spezifikationen. Dazu gehörte die Charakterisierung und die Parameterextraktion des verkleinerten Transistortyps. Die Optimierung des Durchbruchverhaltens einer Diode, die zum Schutz vor Überspannungspulsen eingesetzt wird, konnte durch die Anpassung der Dotierstoffkonzentrationen erreicht werden. Ebenfalls konnte eine Steigerung der Spannungsfestigkeit eines Hochspannungstransistors erzielt werden, indem u. a. der Avalanche-Effekt durch einen besseren Kanalanschluss vermieden wurde. Neben der Optimierung des elektrischen Verhaltens wurde auch das Zuverlässigkeitsverhalten der Bauelemente verbessert. Hierzu gehörte die Optimierung der Oxidqualität, welche durch Getterung von Kontaminationsatomen signifikant gesteigert werden konnte. Weiterhin konnte auch das Zuverlässigkeitsverhalten der Speicherzellen (EEPROM), welches durch die beiden Aspekte der Datenwechselstabilität und des Datenerhalts beschrieben wird, durch geometrische Veränderungen und Abschirmung der Zelle verbessert werden. Ein weiterer wichtiger Aspekt dieser Arbeit war die Entwicklung von Simulationsmodellen bestimmter Bauelemente in einem breiten Temperaturbereich. Zum einen konnte das elektrische Verhalten von Dioden bei Temperaturen zwischen −40 ℃ und 300 ℃ durch ein Makromodell genau nachgebildet werden. Zum anderen konnten die Datenwechselstabilität und der Datenerhalt der Speicherzelle bis zu einer Temperatur von 450 ℃ mithilfe eines Modells korrekt wiedergegeben werden. Die Modelle werden verwendet, um eine Vorhersage über das Verhalten von Bauelementen bei unterschiedlichen Temperaturen zu treffen, dienen als Hilfsmittel zur Optimierung der Bauelemente und sind für die Simulation von Schaltungen notwendig. Weiterhin wurden in der vorliegenden Arbeit neue Bauelemente vorgestellt, die vor allem für den Einsatz in einem breiten Temperaturbereich konzipiert sind. So wurde eine Schutzstruktur vor Überspannungspulsen vorgeschlagen, die bei einer Betriebsspannung von 3,3 V und einer Temperatur bis 250 ℃ eingesetzt werden soll. Dazu wurde entweder der Punch-Through- oder der Floating-Body-Effekt ausgenutzt, um das Bauelement ab einer bestimmten Spannung in den Leitungszustand zu versetzen. Für den Betrieb eines Hochspannungstransistors wurde in dieser Arbeit eine Bauweise vorgeschlagen, die es ermöglicht, die transistorspezifischen Eigenschaften, wie die Schwellenspannung oder den Leckstrom, in Abhängigkeit der Temperatur deutlich zu verbessern. Somit wurden in dieser Arbeit verschiedene kritische Bereiche einer CMOS-Technologie behandelt, die sich beim Hochtemperaturbetrieb ergeben. Dazu wurden Optimierungen im Bezug auf das elektrische Verhalten bzw. die Zuverlässigkeit vorgeschlagen und neue Bauelemente entwickelt, die vor allem für den Betrieb bei hohen Temperaturen ausgelegt sind. Zusätzlich wurden Simulationsmodelle für den erweiterten Temperaturbereich entwickelt, die nicht zuletzt zur Optimierung der Bauelemente beitragen.The present work focuses on the optimization and modeling of devices from a 0.35 μm technology developed for the operation in a wide temperature range from −40 ℃ up to 250 ℃. This technology is a further development of a 1 μm high temperature technology with various modifications in the processing flow. The shrink of the technology node allows to process more complex integrated circuits with a higher device density. For the wide temperature range, a thin film SOI technology is utilized that shows substantial benefits compared to the commonly used bulk technology. The numerous changes in the new technology require adjustment of the electric behavior of different devices to fulfill the specifications. Within the framework of this study one of the tasks was the characterization and the parameter extraction of the downsized transistor type. Further the breakdown behavior of a diode used for ESD protection was optimized by adapting the doping concentration. The breakdown voltage of a high voltage transistor was enhanced by a proper biasing of the channel area. Besides the optimization of the electric behavior the reliability of the devices was improved as well. For this purpose, the oxide quality was optimized by gettering contaminants. Furthermore the reliability of the memory cells (EEPROM) that can be described by the retention and endurance behavior was increased by geometrical optimization and a better isolation of the cell. In addition, simulation models were developed for specific devices to characterize the electric behavior in a wide temperature range. The characteristics of two different diodes at temperatures between −40 ℃ and 300 ℃ were simulated by a macro model. The endurance and retention behavior of a memory cell was also described by a macro model for temperatures up to 450 ℃. The models are used to predict the behavior of the devices at different temperatures, serve as auxiliary tools to optimize the devices and are also used for circuit simulations. Furthermore, new devices are developed in the present work to enable the operation in a wide temperature range. An ESD device is proposed to protect circuits with a low operating voltage of 3.3 V for temperatures up to 250 ℃. For this purpose, the punch through or floating body effect is used to bring the device in a conduction state at a certain trigger voltage. For the operation of high voltage transistor a new design is proposed, which allows to improve the transistor specific properties (for example leakage current or threshold voltage) at high temperatures. In summary, different critical parts of a CMOS technology designed for high temperature applications are investigated in this work. Optimizations with respect to the electric behavior and the reliability are proposed and new devices are developed to improve the performance at high temperatures. Additionally, simulation models are proposed to allow an accurate description of the electrical device behavior in a wide temperature range and which can also be used to optimize the device performance

Electrical overstress and electrostatic discharge failure in silicon MOS devices

This thesis presents an experimental and theoretical investigation of electrical failure in MOS structures, with a particular emphasis on short-pulse and ESD failure. It begins with an extensive survey of MOS technology, its failure mechanisms and protection schemes. A program of experimental research on MOS breakdown is then reported, the results of which are used to develop a model of breakdown across a wide spectrum of time scales. This model, in which bulk-oxide electron trapping/emission plays a major role, prohibits the direct use of causal theory over short time-scales, invalidating earlier theories on the subject. The work is extended to ESD stress of both polarities. Negative polarity ESD breakdownis found to be primarily oxide-voltage activated, with no significant dependence on temperature of luminosity. Positive polarity breakdown depends on the rate of surface inversion, dictated by the Si avalanche threshold and/or the generation speed of light-induced carriers. An analytical model, based upon the above theory is developed to predict ESD breakdown over a wide range of conditions. The thesis ends with an experimental and theoretical investigation of the effects of ESD breakdown on device and circuit performance. Breakdown sites are modelled as resistive paths in the oxide, and their distorting effects upon transistor performance are studied. The degradation of a damaged transistor under working stress is observed, giving a deeper insight into the latent hazards of ESD damage

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields