Polisgenese und Urbanisierung in Aitolien im 5. und 4. Jh. v. Chr.

The ever advance of CMOS digital circuit process leads tothe trend of digitizing an analog signal and performing digitalsignal processing as early as possible in a signal processingsystem, which in turn leads to an increasing requirement onanalog- to-digital converter (ADC). A wireless transceiver is asuch kind of signal processing system. Conventionaltransceivers manipulate (filter, amplify and mix) the signalmostly in analog domain. Since analog filters are difficult todesign onchip, the system integration level is low. Moderntransceivers shift many of these tasks to digital domain, wherethe filtering and channel selection can be realized moreaccurately and more compactly. However the price for the highintegration level is the critical requirement on the ADC,because the simplified analog part sends not only the weaksignal but also the unwanted strong neighboring channel to theADC. In order to digitize the needed signal in the presence ofstrong disturbances, a high dynamic-range and high-speed ADC isneeded. Sigma Delta ADCs are promising candidates for A/D conversionin modern wireless transceivers. They are naturally suitablefor high-resolution narrow-band A/D conversions. With thedevelopment of processing and design techniques, sigma deltaADCs are expanding their applications to moderate-band area,such as wireless communication baseband processing. Currentlymobile communication systems are migrating from 2G to 3G. In 2Gsystems the baseband width is in the order of hundred kHz,while in 3G systems the baseband width is in the order of MHz.To face the challenge of designing a high resolution sigmadelta ADC with large bandwidth, a multi-bit internal quantizeris often used. In this thesis special design considerations onmulti-bit sigma delta modulators are discussed. The biggestdrawback of multi-bit sigma delta modulators isthe need of anextra circuit to attenuate or compensate the internal multi-bitDAC non-linearity. This thesis provides a comprehensiveanalysis of the solution which combines a multi-bit quantizerwith a 1-bit DAC in a sigma delta modulator. The theoreticalanalysis result is verified by measurement results. Anothertopic addressed in the thesis is how to reduce the multi-bitquantizer complexity. It is shown that by using a semiuniformquantizer, the quantizer can reduce its complexity by one-bityet still maintain the same modulator dynamic range. Theperformance of the semi-uniform quantizer is also verified bymeasurement results.NR 2014080

Bit-stream adders and multipliers for tri-level sigma-delta modulators

We propose both adder and multiplier circuits for bit-stream signal processing customized for tri-level sigma-delta modulated signals. These architectures are the 2-bit extensions from the existing 1-bit bit-stream adders and multipliers, and are shown to offer better signal-to-noise performance. Field-programmable gate array implementations then confirm their efficacy. © 2007 IEEE.published_or_final_versio

Delta-Sigma signal processing in control engineering

In modernen Anwendungen werden überabtastende Analog-zu-Digital Umsetzer eingesetzt. Eine besondere Klasse sind die Delta-Sigma-Analog-zu-Digital Umsetzer (ADU). Sie werden bei sehr hohen Abtastfrequenzen betrieben, in der Regel bei dem 64- bis 1024-fachen der Signalfrequenz, dafür besitzen sie eine sehr geringe Quantisierung, bis zu einem Bit. Mit entsprechenden digitalen Filtern lassen sich mit dem Verfahren Wortbreiten von 12 bis 16 Bit erreichen. Allerdings begrenzt dabei das Filter die erzielbare Kleinsignalbandbreite. Mit der weiterentwickelten und vorgestellten ΔΣ Signalverarbeitung (ΔΣSV) kann auf die Filterung verzichtet werden. In dieser Arbeit werden unterschiedliche Verfahren zur ΔΣSV evaluiert. Das Ergebnis stellen sowohl Klassen für lineare, als auch eine Klasse für nichtlineare Operationen dar, die eine gute Abbildungsqualität besitzen und alle Funktionen aus der jeweiligen Klasse abbilden können. Basierend auf diesen Operationen wird die Strom- und Spannungsregelung einer dreiphasigen Last vorgestellt. Zur Umsetzung der hochfrequenten Bitströme in leistungshalbleitertaugliche Schaltfrequenzen wird ein hysteresebasierter Modulator, der echte Raumzeigermodulation mit beiden Nullvektoren beherrscht, eingesetzt. Für diesen wird ein Schaltfrequenzregler vorgestellt und unterschiedliche Stromregler erprobt. Abschließend wird eine drehgeberlose Geschwindigkeitsregelung in ΔΣSV vorgestellt.In modern applications oversampling analog-to-digital converters (ADC) are used. A special class are the Delta-Sigma-ADCs. They operate at very high sampling frequencies, usually at 64 up to 1024 times the signal frequency, but have a very low quantization, down to one bit. With corresponding digital filters, word sizes from 12 to 16 Bit can be achieved. However, the filters limit the achievable small signal bandwidth. In order to ommit these, the ΔΣ signal processing (ΔΣSP) has been developed. In this thesis different methods for ΔΣSP are evaluated. As a result, a class for linear as well as a class for nonlinear operations is presented, which have a good projection quality and can map all functions of the respective class. Based on these operations, the current and voltage regulation of a threephase load is presented. To convert the high-frequency bitstreams into switching frequencies suitable for power semiconductors, a hysteresis-based modulator is presented which outputs true space vector modulation with both zero vectors. For this modulator a switching frequency controller is presented and diferent current controllers are evaluated. Concluding, an encoderless speed control is presented in ΔΣSP

A Single IF FM/AM Decoder using a Sigma-Delta Analog-Digital Converter

This paper describes a digital radio demodulator for broadcast AM/FM receiver applications. The IC is comprised of a Sigma-Delta A/D converter and a digital AM/FM demodulator. The Sigma Delta modulator converts the standard 10.7 MHz IF signal, allowing the use of digital channel-select filtering, providing improved performance over analog filtering. Subsequent demodulation and signal processing are performed digitally, allowing flexibility in the algorithms employed and greater integration with other digital circuitry in the system. There is also a software element to the system, as the stereo decoder and RDS decoding functions are implemented by DSP off-chip rather than on dedicated hardware. Behavioural-level simulations of the system are presented, which show it meets the requirements of 80 db SNR for stereo FM input signals over a 150 kHz bandwidth

Quantization Noise Shaping for Information Maximizing ADCs

ADCs sit at the interface of the analog and digital worlds and fundamentally determine what information is available in the digital domain for processing. This paper shows that a configurable ADC can be designed for signals with non constant information as a function of frequency such that within a fixed power budget the ADC maximizes the information in the converted signal by frequency shaping the quantization noise. Quantization noise shaping can be realized via loop filter design for a single channel delta sigma ADC and extended to common time and frequency interleaved multi channel structures. Results are presented for example wireline and wireless style channels.Comment: 4 pages, 6 figure

An ultra-low-power sigma-delta neuron circuit

Neural processing systems typically represent data using leaky integrate and fire (LIF) neuron models that generate spikes or pulse trains at a rate proportional to their input amplitudes. This mechanism requires high firing rates when encoding time-varying signals, leading to increased power consumption. Neuromorphic systems that use adaptive LIF neuron models overcome this problem by encoding signals in the relative timing of their output spikes rather than their rate. In this paper, we analyze recent adaptive LIF neuron circuit implementations and highlight the analogies and differences between them and a first-order sigma-delta feedback loop. We propose a new sigma-delta neuron circuit that addresses some of the limitations in existing implementations and present simulation results that quantify the improvements. We show that the new circuit, implemented in a 1.8 V, 180 nm CMOS process, offers up to 42 dB signal-to-distortion ratio and consumes orders of magnitude lower energy. Finally, we also demonstrate how the sigma-delta interpretation enables mapping of real-valued recurrent neural network to the spiking framework to emphasize the envisioned application of the proposed circuit.Comment: Submitted to TCAS-II Briefs. Reference code online-https://github.com/manuvn/sigma-delta-neural-networks.gi

Real-time 100-GS/s sigma-delta modulator for all-digital radio-over-fiber transmission

All-digital radio-over-fiber (RoF) transmission has attracted a significant amount of interest in digital-centric systems or centralized networks because it greatly simplifies the front-end hardware by using digital processing. The sigma-delta modulator (SDM)-based all-digital RoF approach pushes the digital signal processing as far as possible into the transmit chain. We present a real-time 100-GS/s fourth-order single-bit SDM for all-digital RoF transmission in the high-frequency band without the aid of analog/optical up-conversion. This is the fastest sigma-delta modulator reported and this is also the first real-time demonstration of sigma-delta-modulated RoF in the frequency band above 24 GHz. 4.68 Gb/s (2.34 Gb/s) 64-QAM is transported over 10-km standard single-mode fiber in the C-band with 6.46% (4.73%) error vector magnitude and 3.13 Gb/s 256-QAM can be even received in an optical back-to-back configuration. The carrier frequency can be digitally tuned at run-time, covering a wide frequency range from 22.75 to 27.5 GHz. Besides, this high-speed sigma-delta modulator introduces less than 1 mu s latency in the transmit chain. Its all-digital nature enables network virtualization, making the transmitter compatible with different existing standards. The prominent performance corroborates the strong competitiveness of this SDM-based RoF approach in high-frequency RoF 5C communication