DESIGN, COMPACT MODELING AND CHARACTERIZATION OF NANOSCALE DEVICES

Electronic device modeling is a crucial step in the advancement of modern nanotechnology and is gaining more and more interest. Nanoscale complementary metal oxide semiconductor (CMOS) transistors, being the backbone of the electronic industry, are pushed to below 10 nm dimensions using novel manufacturing techniques including extreme lithography. As their dimensions are pushed into such unprecedented limits, their behavior is still captured using models that are decades old. Among many other proposed nanoscale devices, silicon vacuum electron devices are regaining attention due to their presumed advantages in operating at very high power, high speed and under harsh environment, where CMOS cannot compete. Another type of devices that have the potential to complement CMOS transistors are nano-electromechanical systems (NEMS), with potential applications in filters, stable frequency sources, non-volatile memories and reconfigurable and neuromorphic electronics

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

By the continuing downscaling of sub-micron transistors in the range of few to one deca-nanometers, we focus on the increasing relative level of the low-frequency noise in these devices. Large amount of published data and models are reviewed and summarized, in order to capture the state-of-the-art, and to observe that the 1/area scaling of low-frequency noise holds even for carbon nanotube devices, but the noise becomes too large in order to have fully deterministic devices with area less than 10nm×10nm. The low-frequency noise models are discussed from the point of view that the noise can be both intrinsic and coupled to the charge transport in the devices, which provided a coherent picture, and more interestingly, showed that the models converge each to other, despite the many issues that one can find for the physical origin of each model. Several derivations are made to explain crossovers in noise spectra, variable random telegraph amplitudes, duality between energy and distance of charge traps, behaviors and trends for figures of merit by device downscaling, practical constraints for micropower amplifiers and dependence of phase noise on the harmonics in the oscillation signal, uncertainty and techniques of averaging by noise characterization. We have also shown how the unavoidable statistical variations by fabrication is embedded in the devices as a spatial “frozen noise”, which also follows 1/area scaling law and limits the production yield, from one side, and from other side, the “frozen noise” contributes generically to temporal 1/f noise by randomly probing the embedded variations during device operation, owing to the purely statistical accumulation of variance that follows from cause-consequence principle, and irrespectively of the actual physical process. The accumulation of variance is known as statistics of “innovation variance”, which explains the nearly log-normal distributions in the values for low-frequency noise parameters gathered from different devices, bias and other conditions, thus, the origin of geometric averaging in low-frequency noise characterizations. At present, the many models generally coincide each with other, and what makes the difference, are the values, which, however, scatter prominently in nanodevices. Perhaps, one should make some changes in the approach to the low-frequency noise in electronic devices, to emphasize the “statistics behind the numbers”, because the general physical assumptions in each model always fail at some point by the device downscaling, but irrespectively of that, the statistics works, since the low-frequency noise scales consistently with the 1/area law

Compact modeling of the rf and noise behavior of multiple-gate mosfets

La reducción de la tecnología MOSFET planar ha sido la opción tecnológica dominante en las últimas décadas. Sin embargo, hemos llegado a un punto en el que los materiales y problemas en los dispositivos surgen, abriendo la puerta para estructuras alternativas de los dispositivos. Entre estas estructuras se encuentran los dispositivos DG, SGT y Triple-Gate. Estas tres estructuras están estudiadas en esta tesis, en el contexto de rducir las dimensiones de los dispositivos a tamaños tales que los mecanismos cuánticos y efectos de calan coro deben tenerse n cuenta. Estos efectos vienen con una seria de desafíos desde el pun to de vista de modelación, unos de los más grandes siendo el tiempo y los recursos comprometidos para ejecutar las simulaciones. para resolver este problema, esta tesis propone modelos comlets analíticos y compactos para cada una de las geometrías, validos desde DC hasta el modo de operación en Rf para los nodos tecnológicos futuros. Dichos modelos se han extendido para analizar el ruido de alta frecuencia en estos diapositivos

Characterization and modeling of low-frequency noise in Hf-based high -kappa dielectrics for future cmos applications

The International Technology Roadmap for Semiconductors outlines the need for high-K dielectric based gate-oxide Metal Oxide Semiconductor Field Effect Transistors for sub-45 nm technology nodes. Gate oxides of hafnium seem to be the nearest and best alternative for silicon dioxide, when material, thermal and structural properties are considered. Usage of poly-Si as a gate electrode material degrades the performance of the device and hence gate stacks based on metal gate electrodes are gaining high interest. Though a substantial improvement in the performance has been achieved with these changes, reliability issues are a cause of concern. For analog and mixed-signal applications, low-frequency (I /f~ noise is a major reliability factor. Also in recent years. low frequency noise diagnostics has become a powerful tool for device performance and reliability characterization. This dissertation work demonstrates the necessity of gate stack engineering for achieving a low I/f noise performance. Changes in the material and process parameters of the devices, impact the 1/f noise behavior. The impact of 1/f noise on gate technology and processing parameters xvere identified and investigated. The thickness and the quality of the interfacial oxide, the nitridation effects of the layers, high-K oxide, bulk properties of the high-K layer. percentage of hafnium content in the high-K, post deposition anneal (PDA) treatments, effects of gate electrode material (poly-silicon. fully silicided or metal). Gate electrode processing are investigated in detail. The role of additional interfaces and bulk layers of the gate stack is understood. The dependence of low-frequency noise on high and low temperatures was also investigated. A systematic and a deeper understanding of these parameters on 1/f noise behavior are deduced which also forms the basis for improved physics-based 1/f noise modeling. The model considers the effect of the interfacial layer and also temperature, based on tunneling based thermally activated model. The simulation results of improved drain-current noise model agree well with the experimentally calculated values

Nanowire Transistors and RF Circuits for Low-Power Applications

The background of this thesis is related to the steadily increasing demand of higher bandwidth and lower power consumption for transmitting data. The work aims at demonstrating how new types of structures, at the nanoscale, combined with what is referred to as exotic materials, can help benefit in electronics by lowering the consumed power, possibly by an order of magnitude, compared to the industry standard, silicon (Si), used today. Nanowires are semiconductor rods, with two dimensions at the nanoscale, which can be either grown with a bottom-up technique, or etched out with a top-down approach. The research interest concerning nanowires has gradually increasing for over two decades. Today, few have doubts that nanowires represent an attractive alternative, as scaling of planar structures has reached fundamental limits. With the enhanced electrostatics of a surrounding gate, nanowires offer the possibility of continued miniaturization, giving semiconductors a prolonged window of performance improvements. As a material choice, compound semiconductors with elements from group III and V (III-Vs), such as indium arsenide (InAs), have the possibility to dramatically decrease power consumption. The reason is the inherent electron transport properties of III-Vs, where an electron can travel, in the order of, 10 times faster than in Si. In the projected future, inclusion of III-Vs, as an extension to the Si-CMOS platform, seems almost inevitable, with many of the largest electronics manufacturing companies showing great interest. To investigate the technology potential, we have fabricated InAs nanowire metal-oxide-semiconductor field effect transistors (NW-FETs). The performance has been evaluated measuring both RF and DC characteristics. The best devices show a transconductance of 1.36 mS/µm (a device with a single nanowire, normalized to the nanowire circumference) and a maximum unilateral power gain at 57 GHz (for a device with several parallel nanowires), both values at a drive voltage of 0.5 V. The performance metrics are found to be limited by the capacitive load of the contact pads as well as the resistance in the non-gated segments of the nanowires. Using computer models, we have also been able to extract intrinsic transport properties, quantifying the velocity of charge carrier injection, which is the limiting property of semi-ballistic and ballistic devices. The value for our 45-nm-in-diameter nanowires, with 200 nm channel length, is determined to 1.7∙107 cm/s, comparable to other state-of-the-art devices at the same channel length. To demonstrate a higher level of functionality, we have connected several NW-FETs in a circuit. The fabricated circuit is a single balanced differential direct conversion mixer and is composed of three stages; transconductance, mixing, and transimpedance. The basic idea of the mixer circuit is that an information signal can either be extracted from or inserted into a carrier wave at a higher frequency than the information wave itself. It is the relative size of the first and the third stage that accounts for the circuit conversion gain. Measured circuits show a voltage conversion gain of 6 dB and a 3-dB bandwidth of 2 GHz. A conversion mixer is a vital component when building a transceiver, like those found in a cellphone and any other type of radio signal transmitting device. For all types of signals, noise imposes a fundamental limitation on the minimal, distinguishable amplitude. As transistors are scaled down, fewer carriers are involved in charge transport, and the impact of frequency dependent low-frequency noise gets relatively larger. Aiming towards low power applications, it is thus of importance to minimize the amount of transistor generated noise. Included in the thesis are studies of the level and origin of low-frequency 1/f-noise generated in NW-FETs. The measured noise spectral density is comparable to other non-planar devices, including those fabricated in Si. The data suggest that the level of generated noise can be substantially lowered by improving the high-k dielectric film quality and the channel interface. One significant discovery is that the part of the noise originating from the bulk nanowire, identified as mobility fluctuations, is comparably much lower than the measured noise level related to the nanowire surface. This result is promising as mobility fluctuations set the lower limit of what is achievable within a material system

Flexible Ultralow-Power Sensor Interfaces for E-Skin

Thin-film electronics has hugely benefitted from low-cost processes, large-area processability, and multi-functionality. This has not only stimulated innovation in display and sensor technology, but has also demonstrated great potential for integration of components for human-machine interfaces. For electronics to be deployed as sensor interfaces and signal processing, the quest for low power is compelling due to the inherently limited battery lifetime. This review will present the state-of-the-art in thin film electronics and demonstrate examples of low-cost printable transistors and biosensors that are flexible/stretchable for wearable and other applications. Ultralow power design for thin-film transistors will be discussed from the standpoint of reducing both operating voltage and operating current, taking into account the challenges in meeting frequency requirements. Compact models for circuit design will be reviewed along with new insights into ultralow power transistors and high gain amplifier circuits. Finally, a concept for an integrated system comprising sensors and interfacing circuits will be demonstrated, which has the potential to enable battery-less operation.EPSRC under Project EP/M013650/1 EU under Projects DOMINO 645760, 1D-NEON 685758 and BET-EU 692373 IEEE Electron Devices Society PhD Student Fellowship China Scholarship Counci

Random dopants and low-frequency noise reduction in deep-submicron MOSFET technology

The future of mixed-signal, memory, and microprocessor technologies are dependent on ever increasing analog and digital integration, higher cell densities, and demand for more processing power. As a result MOSFET device dimensions continue to shrink to meet these demands. A side effect of device scaling is increased variability at each technological node which affects both analog and digital circuits in terms of decreased yields, performance, and noise margins. At deep sub-micron dimensions the Low-Frequency Noise (LFN) of the MOSFET is dominated by the influence of one or more active traps capturing and emitting charge to and from the oxide creating wide variations in the LFN from otherwise identical devices. Additionally, the random position of dopant atoms near the Si/SiO₂ interface create a potential landscape that induces regions of high and low conductivity which in turn causes a situation where the current is no longer uniform in the device, but consist of individual current paths or percolating currents. The coupling between the random variation of the percolation current and active traps in the oxide are responsible for the large spread ( > 3 orders of magnitude) in the noise characteristics observed in deep sub-micron MOSFET devices. The compact LFN model presented here accounts for the action of traps on percolating currents in deep-sub-micron and nano-scale MOSFETs. Two schemes for reduction of LFN are studied based on the smoothing of the surface potential. First, noise reduction is demonstrated with measurements on sub-micron MOSFETs with forward substrate bias. Secondly, the model is further verified through the reduction of noise by the removal of dopant atoms near the Si/SiO₂ interface of the device. Both schemes result in a lower noise and threshold device. Finally, these experimental findings are applied to a 2.2μm 2 MP CMOS image sensor. From the temporal noise measurements on threshold implant process splits, the image sensor noise has been significantly reduced as a direct result of fundamentals described by this MOSFET LFN model and further proves the validity of these findings.Keywords: Low-Frequency Noise, MOSFET, sub-micron, RT

Low-Frequency Noise in TFETs

Nanowire tunnel field-effect transistors (TFETs) were investigated by carrying out noise measurements and low-temperature DC measurements. The TFET tunnelling junction was realised by a GaSb/InAs heterojunction resulting in a broken band gap. TFET noise currents were measured at frequencies between 10 Hz and 1 kHz. The results imply that noise in TFETs at the current state of development is dominated by generation-recombination processes caused by traps in the gate oxide. Trap densities between 10^20 cm^-3 eV^-1 and 10^22 cm^-3 eV^-1 were extracted from the noise measurements. The temperature-dependent DC measurements show that the TFETs' off-current is sensitive to the temperature, with lower off-currents at lower temperatures. This indicates that it is not only the tunnelling junction which is governing the off-current. It is concluded that in the devices' off-state electrons can still tunnel into the channel area through the broken band gap but require additional thermionic excitation over the bent channel conduction band to constitute a current.The ever-growing demand for electronic devices in all areas of our lives can only be satisfied due to the constant development of today’s most essential of all active electronic devices – the metal-oxide-semiconductor field-effect transistor (MOSFET). However, its further development is drawing to an end, so coming up with alternatives is of utmost importance. One of the most promising ones is the tunnel field-effect transistor (TFET). A MOSFET basically is an electrical switch. The current between two of the device’s contacts – source and drain – can be controlled by a third contact, the gate. In digital applications, such as all our computers and smartphones, MOSFETs only switch between an on- and an off-state, meaning flowing current or almost no current, respectively. The ability to switch between these two states as fast as possible is what governs a MOSFET’s speed and energy-efficiency. Over the last 50 years MOSFETs have undergone constant development to increase these measures. Due to the underlying physical principles that MOSFETs are based on, this development is drawing to an end. In a MOSFET electrons have to overcome an energy barrier to establish a current. With the gate contact this barrier can be raised (off-state) or lowered (on-state). This principle establishing the current is at the same time the principle which limits further scaling of MOSFETs as there are always a few electrons which can overcome the barrier – even in the device’s off-state. The idea for TFETs to overcome this limit is to control the current by opening or closing a narrow gap in the energy structure of the device. Instead of overcoming a barrier the electrons have to tunnel through it. In contrast to the MOSFET structure the electrons on the source side of the TFET structure face a restriction from the top which reduces the off-current. In my thesis I contribute to the development of TFETs as successors of or complements to MOSFETs by examining electrical noise and the current temperature dependence in TFETs. A well-known form of electrical noise is noise which finds its way into an audio signal (e. g. buzzing speakers). However, noise is present in all electrical signals and examining the noise in TFETs gives information about which parts of the devices require particular improvement to finally lead to industrially applicable TFETs benefitting the broad public

A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy