Efficient Spectral Power Estimation on an Arbitrary Frequency Scale

The Fast Fourier Transform is a very efficient algorithm for the Fourier spectrum estimation, but has the limitation of a linear frequency scale spectrum, which may not be suitable for every system. For example, audio and speech analysis needs a logarithmic frequency scale due to the characteristic of a human’s ear. The Fast Fourier Transform algorithms are not able to efficiently give the desired results and modified techniques have to be used in this case. In the following text a simple technique using the Goertzel algorithm allowing the evaluation of the power spectra on an arbitrary frequency scale will be introduced. Due to its simplicity the algorithm suffers from imperfections which will be discussed and partially solved in this paper. The implementation into real systems and the impact of quantization errors appeared to be critical and have to be dealt with in special cases. The simple method dealing with the quantization error will also be introduced. Finally, the proposed method will be compared to other methods based on its computational demands and its potential speed

Fast Algorithms for the Real Discrete Fourier Transform

Fast algorithms for the computation of the real discrete Fourier transform (RDFT) are discussed. Implementations based on the RDFT are always efficient whereas the implementations based on the DFT are efficient only when signals to be processed are complex. The fast real Fourier (FRFT) algorithms discussed are the radix-2 decimation-in-time (DIT), the radix-2 decimation-in-frequency (DIF), the radix-4 DIT, the split-radix DIT, the split-radix DIF, the prime-factor, the Rader prime, and the Winograd FRFT algorithms

Determining Angular Frequency from a video with a Generalized Fast Fourier Transform

Suppose we are given a video of a rotating object and suppose we want to determine the rate of rotation solely from the video itself and its known frame rate. In this thesis, we present a new mathematical operator called the Geometric Sum Transform (GST) that can help one determine the angular frequency of the object in question. The GST is a generalization of the discrete Fourier transform (DFT) and as such, the two transforms have much in common. However, whereas the DFT is applied to a sequence of scalars, the GST can be applied to a sequence of vectors. Most importantly, we show that the GST, like the DFT, can (1) be used to estimate frequency and (2) can be computed surprisingly quickly. Indeed, we provide a Fast Geometric Sum Transform (FGST) algorithm that computes the GST in O(N logN) matrix-vector multiplications, where N is the number of images in the video sequence. This is a vast improvement over the O(N2) such multiplications required for a direct computation of the GST. The remainder of this thesis is devoted to proving other properties of the GST and giving proof-of-concept numerical examples

An equalization technique for high rate OFDM systems

In a typical orthogonal frequency division multiplexing (OFDM) broadband wireless communication system, a guard interval using cyclic prefix is inserted to avoid the inter-symbol interference and the inter-carrier interference. This guard interval is required to be at least equal to, or longer than the maximum channel delay spread. This method is very simple, but it reduces the transmission efficiency. This efficiency is very low in the communication systems, which inhibit a long channel delay spread with a small number of sub-carriers such as the IEEE 802.11a wireless LAN (WLAN). To increase the transmission efficiency, it is usual that a time domain equalizer (TEQ) is included in an OFDM system to shorten the effective channel impulse response within the guard interval. There are many TEQ algorithms developed for the low rate OFDM applications such as asymmetrical digital subscriber line (ADSL). The drawback of these algorithms is a high computational load. Most of the popular TEQ algorithms are not suitable for the IEEE 802.11a system, a high data rate wireless LAN based on the OFDM technique. In this thesis, a TEQ algorithm based on the minimum mean square error criterion is investigated for the high rate IEEE 802.11a system. This algorithm has a comparatively reduced computational complexity for practical use in the high data rate OFDM systems. In forming the model to design the TEQ, a reduced convolution matrix is exploited to lower the computational complexity. Mathematical analysis and simulation results are provided to show the validity and the advantages of the algorithm. In particular, it is shown that a high performance gain at a data rate of 54Mbps can be obtained with a moderate order of TEQ finite impulse response (FIR) filter. The algorithm is implemented in a field programmable gate array (FPGA). The characteristics and regularities between the elements in matrices are further exploited to reduce the hardware complexity in the matrix multiplication implementation. The optimum TEQ coefficients can be found in less than 4µs for the 7th order of the TEQ FIR filter. This time is the interval of an OFDM symbol in the IEEE 802.11a system. To compensate for the effective channel impulse response, a function block of 64-point radix-4 pipeline fast Fourier transform is implemented in FPGA to perform zero forcing equalization in frequency domain. The offsets between the hardware implementations and the mathematical calculations are provided and analyzed. The system performance loss introduced by the hardware implementation is also tested. Hardware implementation output and simulation results verify that the chips function properly and satisfy the requirements of the system running at a data rate of 54 Mbps

FFT and FIR Filter implementations for the DSL MODEMS

Broad band digital communication that operates over a standard copper wires. It requires the DSL modems which splits the transmissions into 2 frequency bands. The lower frequencies for voice and the higher frequencies for digital data (internet) in order to transmit the data to larger distances through a copper cable we need modulation techniques. Generally in this DSL modems modulation used is QAM technique. The output of the QAM is complex data this complex data we cannot transfer directly through a copper cable because the data should be in time domain or otherwise the phase of the data which is in frequency domain can be lost, in copper cable so this data should be converted in time domain by using IDFT technique. As IDFT requires more number of complex multiplications and more number of complex additions in comparison to IFFT so to reduce the additions and multiplications IFFT technique is used. At the receiver side we can retrieve the same data by using FFT technique. In this section the implemented FFT architecture is fully efficient and this architecture will require less area. And before we have to transmit through the copper line we have to do interpolation or decimation by using the Filtering operation. The implemented poly phase architecture for the filtering is fully efficient, symmetrical and it requires less number of multipliers

Energy area and speed optimized signal processing on FPGA

Matrix multiplication and Fast Fourier transform are two computational intensive DSP functions widely used as kernel operations in the applications such as graphics, imaging and wireless communication. Traditionally the performance metrics for signal processing has been latency and throughput. Energy efficiency has become increasingly important with proliferation of portable mobile devices as in software defined radio. A FPGA based system is a viable solution for requirement of adaptability and high computational power. But one limitation in FPGA is the limitation of resources. So there is need for optimization between energy, area and latency. There are numerous ways to map an algorithm to FPGA. So for the process of optimization the parameters must be determined by low level simulation of each of the designs possible which gives rise to vast time consumption. So there is need for a high level energy model in which parameters can be determined at algorithm and architectural level rather than low level simulation. In this dissertation matrix multiplication algorithms are implemented with pipelining and parallel processing features to increase throughput and reduce latency there by reduce the energy dissipation. But it increases area by the increased numbers of processing elements. The major area of the design is used by multiplier which further increases with increase in input word width which is difficult for VLSI implementation. So a word width decomposition technique is used with these algorithms to keep the size of multipliers fixed irrespective of the width of input data. FFT algorithms are implemented with pipelining to increase throughput. To reduce energy and area due to the complex multipliers used in the design for multiplication with twiddle factors, distributed arithmetic is used to provide multiplier less architecture. To compensate speed performance parallel distributed arithmetic models are used. This dissertation also proposes method of optimization of the parameters at high level for these two kernel applications by constructing a high level energy model using specified algorithms and architectures. Results obtained from the model are compared with those obtained from low level simulation for estimation of error