Behavior of Space Charge in Polyimide and the Influence on Power Semiconductor Device Reliability

Polyimide is widely used in film form as a passivation material for power semiconductor devices such as Si, SiC, and GaN. The magnitude of the electric field at the edge termination area of these semiconductor devices is becoming higher due to the increase of operational voltage and/or demand for shrinking the edge termination area to increase device active area. Hence, it is concerned that the accumulation of space charge in the encapsulation and passivation material may affect the insulation performance of these devices, for example, the degradation of withstand voltage due to distortion of the internal electric field caused by space charge accumulation. To design space charge resistance of semiconductor devices, it is important to understand the space charge behavior in polyimide films with a thickness of several to several tens of micrometers. This chapter addresses practical implementation, specifications, and issues on space charge in polyimide insulation on power semiconductor devices focusing on the space charge measurements in thin polyimide films using the latest developed LIMM method and DC conductivity measurements

Influence of material quality and process-induced defects on semiconductor device performance and yield

An overview of major causes of device yield degradation is presented. The relationships of device types to critical processes and typical defects are discussed, and the influence of the defect on device yield and performance is demonstrated. Various defect characterization techniques are described and applied. A correlation of device failure, defect type, and cause of defect is presented in tabular form with accompanying illustrations

Evaluation of Plasma Charging Damage in Ultrathin Gate Oxides

Abstract-Monitoring of plasma charging damage in ultrathin oxides (e.g., <4 nm) is essential to understand its impact on device reliability. However, it is observed that the shift of several device parameters, including threshold voltage, transconductance, and subthreshold swing, are not sensitive to plasma charging and thus not suitable for this purpose. Consequently, some destructive methods, such as the charge-to-breakdown measurement, are necessary to evaluate plasma damage in the ultrathin oxides. Index Terms-Dielectric breakdown, plasma materialsprocessing applications, semiconductor device reliability

An On-Chip Delay Measurement Technique for Small-Delay Defect Detection using Signature Registers

This paper presents a delay measurement technique using signature analysis, and a scan design for the proposed delay measurement technique to detect small-delay defects. The proposed measurement technique measures the delay of the explicitly sensitized paths with the resolution of the on-chip variable clock Generator. The proposed scan design realizes complete on-chip delay measurement in short measurement time using the proposed delay measurement technique and extra latches for storing the test vectors. The evaluation with Rohm 0.18- m process shows that the measurement time is 67.8% reduced compared with that of the delay measurement with standard scan design on average. The area overhead is 23.4% larger than that of the delay measurement architecture using standard scan design, and the difference of the area overhead between enhanced scan design and the proposed method is 7.4% on average. The data volume is 2.2 times of that of test set for normal testing on average

Dielectric relaxation and Charge trapping characteristics study in Germanium based MOS devices with HfO2 /Dy2O3 gate stacks

In the present work we investigate the dielectric relaxation effects and charge trapping characteristics of HfO2 /Dy2O3 gate stacks grown on Ge substrates. The MOS devices have been subjected to constant voltage stress (CVS) conditions at accumulation and show relaxation effects in the whole range of applied stress voltages. Applied voltage polarities as well as thickness dependence of the relaxation effects have been investigated. Charge trapping is negligible at low stress fields while at higher fields (>4MV/cm) it becomes significant. In addition, we give experimental evidence that in tandem with the dielectric relaxation effect another mechanism- the so-called Maxwell-Wagner instability- is present and affects the transient current during the application of a CVS pulse. This instability is also found to be field dependent thus resulting in a trapped charge which is negative at low stress fields but changes to positive at higher fields.Comment: 27pages, 10 figures, 3 tables, regular journal contribution (accepted in IEEE TED, Vol.50, issue 10

Adhesion enhancement for electroless plating on mold compound for EMI shielding with industrial test compliance

In the manufacturing process, metal capping for EMI shielding is done during the integrated circuit (IC) assembly process, which hinders the attempt of reducing the size of electronic device and also incurs higher cost of assembly. Therefore direct deposition of metal on IC mold compound is desirable. Conventional metal plating techniques, however fail tape test. This paper studies the condition of plating metal directly onto surface of mold compound with the enhancement of novel non-etching adhesion promoter CovaBond MRTM. By plating direct onto mold compound, the shielding capping task can be done in array form before the die saw process in IC manufacturing (before IC assembly), which reduce the thickness and dimension of chip and improves design flexibility of circuit board as well as reduce the manufacturing cost. The industrial test results in this paper have proven the performance of the enhanced metal plating technique